We often hear cases that during board debug the Lattice FPGA device is getting very hot. Most often this due to the power of the VCCIO rails not matching the programming of the device. Here is an example case. Let's say the customer is using the following arrangement of bank voltages.
BANK1 3.3V
BANK2 1.8V
BANK3 1.8V
BANK6 2.5V
BANK7 2.5V
With this arrangement on the board the customer wants to create a debug FPGA design utilizing only BANK2 for a memory interface on the board. The customer creates the small design and does not place any pins in the other banks. By default ispLEVER places all unused banks in a defualt power state. This default may or may not match the board design. When this new debug bitstream is downloaded to the board there could be a voltage conflict. With this new debug bitstream we could now have 3.3V driving a 2.5V BANK1. The FPGA device will dissapate the power difference. To eliminate this common occurance we suggest using the BANK preference. This preference allows the user to set the bank voltage directly. If a bank is not used now the BANK preference will be used rather than taking the default voltage. Below is an example of the BANK preference.
BANK 1 VCCIO 3.3 V;
The BANK preference is also useful as a method for making sure all of the IO assignments match the voltage on the board as well. ispLEVER/Diamond will make sure that all of the IO assignments match the BANK voltage set in the preference file. This way you can be sure that your FPGA design meets your board voltages.