Will the PLL in my FPGA work using a 25MHz input clock with a duty cycle of 33%(low) or 66%(high)?
The PLLs in most Lattice FPGAs should operate correctly using a 25 MHz input clock with duty cycles of 33%(low) or 66%(high).
Check the data sheet for the specific FPGA you are using to determine the operating limits of the PLL. Look in the data sheet under the "DC and Switching Characteristics" section for the PLL operating limits. The input clock frequency must be within the listed input frequency range for the PLL.
The duty cycle is not listed in the data sheet explicitly. The input clock cannot exceed the minimum clock high or low time as given in the data sheet (0.5 ns is a typical value). Multiply the duty cycle by the clock period to determine the high and low times for the input clock.
Using the 25 MHz (40 ns period) input clock example, a 33% low time is 13.2 ns (40 * 0.33) which provides plenty of margin over the data sheet specification of 0.5 ns.