The Field-Oriented Control (FOC) Motor Control reference design comprises a complete RISC-V embedded system integrated with the FOC Motor Control IP. A RISC-V MC CPU core is used in the system to configure and initialize the FOC Motor Control IP registers. The FOC Motor Control IP is built with the combination of a custom register transfer level (RTL) IP core and MATLAB-generated modules. This reference design includes the MATLAB model, which allows you to generate hardware description language (HDL) code using the MATLAB HDL coder. The generated MATLAB HDL modules are instantiated in the FOC Motor Control IP. This reference design also includes a graphical user interface (GUI) that allows the host PC to communicate with the Lattice Certus™-NX FPGA device through the universal asynchronous receiver transmitter (UART) interface.