IEEE 1588 Syn1588®Clock_M IP核

Features

• Supports 10/100 Mbit/s half & full duplex modes
• Delivered with PTP Version 1.0 and version 2.0 stack (Linux or Windows®)
• Supports SPI cascade and independent slave mode
• SPI data rates up to 20 Mbit/sec
• 16-bit SPI data transfers, 32 bit interface to the internal SPI controller
• 1 pps output
• 2 period timer output with a period ranging from 14,000 sec down to 100 nsec.
• 2 event input which draws a time stamp and stores it in the time stamp FIFO
• Events may be processed at a burst rate of 5 MHz, depentent on host processor speed
• 2 trigger output signal which may be used to generate a signal transition at a given point in time
• All event, period, and trigger signals are strictly synchronous to the internal high accuracy clock
• Delivered with test bench, 100% code coverage guaranteed
• Optional support of GPS timing receivers
• RMII Interface option available upon request

For a complete list of features, download the datasheet

Applications

• Test and Measurement
• Industrial Automation and Control
• Telecom
• Military
• Power Industry