IEEE 1588 Syn1588®Clock_M Core

Oregano Systems LogoThe SYN1588®Clock_M IP-core provides highly accurate clock synchronization compliant to the IEEE 1588 standard version 1.0 and 2.0 for Industrial Ethernet applications. It provides a high resolution, high accuracy hardware clock which uses a 96-bit wide adder based clock architecture allowing supporting input clock frequencies in the range of 10 — 200 MHz. Furthermore the SYN1588 Clock_M comprises an MII-Scanner unit, which scans all Ethernet traffic in search for IEEE 1588 synchronization packets. Upon detection of any such packet it draws a 96-bit wide time stamp from the local clock any copies it together with status and identification data into a time-stamp FIFO.

Evaluation and Licensing Terms

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  • Supports 10/100 Mbit/s half & full duplex modes
  • Delivered with PTP Version 1.0 and version 2.0 stack (Linux or Windows®)
  • Supports SPI cascade and independent slave mode
  • SPI data rates up to 20 Mbit/sec
  • 16-bit SPI data transfers, 32 bit interface to the internal SPI controller
  • 1 pps output
  • 2 period timer output with a period ranging from 14,000 sec down to 100 nsec.
  • 2 event input which draws a time stamp and stores it in the time stamp FIFO
  • Events may be processed at a burst rate of 5 MHz, depentent on host processor speed
  • 2 trigger output signal which may be used to generate a signal transition at a given point in time
  • All event, period, and trigger signals are strictly synchronous to the internal high accuracy clock
  • Delivered with test bench, 100% code coverage guaranteed
  • Optional support of GPS timing receivers
  • RMII Interface option available upon request

For a complete list of features, download the datasheet


  • Test and Measurement
  • Industrial Automation and Control
  • Telecom
  • Military
  • Power Industry

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Block Diagram

This diagram shows the Syn1588 Clock_M IP Core highlighted in green and how it is connected into the communication system.

Performance and Size

The following are typical performance and utilization results.

Lattice Device Slices LUTs REGs EBRs fMAX (MHz)
XP 2178 2866 1941 2 75
XP2 2069 2834 1941 2 125

Ordering Information

This IP core is supported and sold by Oregano Systems, contact Oregano Systems at or visit their website at for more information.


Quick Reference
Oregano IEEE 1588 Syn1588 Clock_M Data Sheet
The SYN1588®Clock_M IP-core provides highly accurate clock synchronization compliant to the IEEE 1588 standard version 1.0 and 2.0 for industrial Ethernet applications.
1/22/2008 PDF 74.3 KB

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