Lattice Synthesis Engine (LSE)

Boost design performance and lower solution cost: Design optimizations performed by synthesis while the design is targeted to the FPGA directly impact the design’s operating performance and its cost. LSE applies a unique recipe, specifically tuned to Lattice FPGA devices.

Easy to try: Full Verilog and VHDL language support, combined with industry standard attributes and SDC constraints enables you to easily run your design through LSE and see if your results are better. It is available to use from both Diamond and iCEcube2.

Road-tested: LSE has been included with Diamond and been in active customer use since 2010. LSE was added to iCEcube2 in early 2013.

Features

Support for MachXO, MachXO2, MachXO3L, ECP5 and iCE device families
Fully integrated into the Diamond and iCEcube2 design environments. Easy to switch between using Synplify Pro and LSE for the synthesis step.
Support for industry standard Verilog and VHDL language (including mixed), along with industry standard attributes and SDC constraints. Enables the user to easily synthesize existing designs using LSE.
GUI tool support for constraint entry (LDC Editor) and schematic netlist viewing & analysis (Netlist Analyzer) reduces the time required for design entry and analysis.
Choice of optimization goals: Area, Balanced, Timing enables the user to highlight which design goals should be emphasized.
See full list of features below

Why Synthesis Choice Matters

Synthesis is a critical step to convert a design from its HDL to the bits used to program the FPGA. A single synthesis tool cannot create the best results for all architectures. Differences in the order that optimizations are applied, and differences in the scope of architectures supported can both result in different results. The synthesis step has the most potential to improve the quality of results in FPGA design. Even if timing is met, further optimization in synthesis might enable targeting a lower cost, lower speed-grade FPGA which can save 15%-30% on costs.

Synthesis quality of results (QoR) is affected by the design snapshot after the HDL parsing, the tool flow, and the order in which the optimizations executed. Because of this some tools may perform better on some set of designs than other tools. Having a choice allows a designer to see design performance on different tools with different commercial options before finalizing the design.

LSE Technology

Lattice Synthesis Engine (LSE) is a logic-synthesis tool designed specifically to produce the best possible results for Lattice’s FPGAs. It synthesizes HDL designs to netlist files constructed with Lattice specific primitives. LSE converts description of digital system to the actual high performance circuits of Lattice technology, recognizing and implementing high-level abstract structures like RAMs, ROMs, finite state machines (FSMs), arithmetic operators, and other elements.

The tool is designed to optimize a given HDL design to specific performance goals: Area, Timing or Balanced. The tool optimizes the design according to user design constraints. Constraint entry is enabled and simplified by the graphical user interface (LDC Editor), which extracts and displays all the relevant design information so user can quickly specify accurate design constraints. The constraints convey performance requirements and optimization options to the optimization engines. Users can view and analyze their design as a schematic using the Netlist Analyzer tool. This is an effective way to quickly analyze the post-synthesis results.

After the optimization process is complete, LSE generates a netlist ready for Map, and Place & Route steps of the FPGA design flow. LSE generates the output in ngd format, which is a fully complete netlist (no black boxes). The option of generating an EDIF netlist is also available. LSE is tightly integrated within the Lattice Diamond environment, making it simple and easy to use.

LSE Development

LSE has been developed and validated for many years. It was first publically released in Diamond 1.1 on November 8, 2010 as beta for Lattice MachXO & MachXO2 devices. The tool has been continuously tested and refined by the internal QA & Applications, and customers over each subsequent Diamond and iCEcube2 release. Since 2008, LSE has been tested and validated with numerous design suites such as basic logic cases, standard benchmark suites, communication prototypes, board demos and IPs. LSE has shown consistently excellent results on XO/XO2 benchmarking suites. Over the last couple of years multiple field evaluations were launched with LSE to increase customer usage. In the process, many customer designs have been collected, tested and included in Lattice internal benchmarking. Currently more than 20,000 unit test cases are run with LSE to validate QoR and functional verification on weekly basis.