SPI Master IP Core

Control for SPI Slave Devices

The Serial Peripheral Interface (SPI) is a high-speed synchronous, serial, full-duplex interface that allows a serial bit stream of configured length (8, 16, 24, 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The Lattice SPI Master IP Core is normally used to communicate with external SPI slave devices such as display drivers, SPI EPROMS, and analog-to-digital converters.

Features

  • Supports four-wire SPI interface (SCLK, SS, MOSI, MISO)
  • Configurable SPI data width (8, 16, 24, or 32 bits wide)
  • Supports Transmit FIFO and Receive FIFO with configurable depth
  • Supports all SPI Clocking Modes (combination of Clock Polarity and Clock Phase)
  • Selectable memory-mapped slave Interface: AHB-Lite, APB or LMMI

Jump to

Block Diagram

Performance and Size

Targeted Device LFMXO5-25-9BBG400I LFCPNX-100-9BBG484I LFD2NX-40-9BG256I LIFCL-40-9BG400I
Configuration Clk Fmax (MHz)* Registers LUTs EBRs Clk Fmax (MHz)* Registers LUTs EBRs Clk Fmax (MHz)* Registers LUTs EBRs Clk Fmax (MHz)* Registers LUTs EBRs
Default 152.56 418 618 2 146.31 418 618 2 155.74 418 618 2 165.1 418 618 2
Interface: APB,
Others = Default
170.77 296 439 2 164.12 296 439 2 137.95 296 439 2 143.28 296 439 2
Interface: LMMI,
Others = Default
200.00 293 416 2 200.00 293 416 2 197.51 293 416 2 200.00 293 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default
147.34 567 754 2 140.61 567 754 2 153.75 567 754 2 172.27 567 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default
165.56 482 712 0 163.75 482 712 0 185.22 482 712 0 172.59 482 712 0

Note: Fmax is generated when the FPGA design only contains SPI Master IP Core, and the target frequency is 50 MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
SPI Master IP Core - Lattice Radiant Software
FPGA-IPUG-02069 1.7 6/23/2021 PDF 1.4 MB
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