iCE40 UltraPlus

ML/AI Low Power FPGA

Related Products


iCE40 UltraPlus Mobile Development Platform

Low Power Connectivity and Computing – With the rising complexity of systems used to power smart homes, factories and cities, the iCE40 UltraPlus FPGA can solve connectivity issues with a wide variety of interfaces and protocols and provide the low power computational resources for higher levels of intelligence.

Edge Intelligent FPGA – The iCE40 UltraPlus FPGA with 5k lookup tables (LUTs) is able to implement Neural Networks for pattern matching necessary to bring always-on intelligence to the edge. Optimized for best-in-class power, designers can eliminate latency associated with cloud intelligence while keeping the overall system solution cost low.

Flexible Package Options – Multiple package are available to fit a wide range of applications needs. From an ultra-small 2.15 x 2.50 mm WLCSP package optimized for consumer and IoT devices, to a 0.5 mm pitch 7 x 7 mm QFN for cost optimized applications.

Features

  • Flexible logic architecture with 2800 or 5280 4 input LUTs, customizable I/O, up to 80 kbits of embedded dual port memory and 1 Mbit of embedded single port memory
  • Ultra-low power advanced process with static current as low as 75 uA and 1-10 mA active current for most applications
  • High performance signal processing using DSP blocks with multiply and accumulate functions
  • Soft Neural Network IPs and compiler for flexible Machine Learning/AI implementation
  • FPGA design tools, demos and reference designs to kick start designs
ACE 2017 Finalist Award 

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iCE40 UltraPLus Device Selection Guide
Parameter UP3K UP5K
Density LUTs 2800 5280
NVCM Yes Yes
Static Current (uA)
 75 75
EBR RAM (kbits) 80 120
SPRAM (kbits) 1024 1024
PLL 1 1
I2C Core 2 2
SPI Core 2 2
Oscillator (10 kHz) 1 1
Oscillator (48 MHz) 1 1
24 mA Drive 3 3
500 mA Drive - -
16 x 16 Multiply & 32 bit Accumulator Blocks 4 8
PWM Yes Yes
0.4 mm Spacing Total I/O + Dedicated Inputs1,2
  UP3K UP5K
30-ball WLCSP (2.15 x 2.55 mm) 21 21
0.5 mm Spacing Total I/O + Dedicated Inputs1,2
  UP3K UP5K
48-pin QFN (7 x 7 mm) - 39

1. Total I/O include Dedicated I/O
2. Dedicated I/O are defined to be pins that are dedicated and cannot be used by user logic after configuration

Example Solutions

Create differentiated products by using Lattice IPs and Reference Designs.

Click Here For More IP and Reference Designs

Binarized Neural Network (BNN) Accelerator IP Block DiagramExpand Image

Binarized Neural Network (BNN) Accelerator IP

  • Take advantage of the FPGA’s parallel processing capability to implement machine learning algorithms.
  • Enables implementation of BNNs that have power consumption in the mW range.
Key Phrase Detection Block DiagramExpand Image

Key Phrase Detection – Lattice SensAI

  • Enable systems to always search for key phrases using a digital microphone input.
  • Consumes less than 1 mW of average power.
Face Detect Block DiagramExpand Image

Human Face Detection

  • Enable artificial intelligence with an always-on image sensor, while consuming less than 1 mW of active power.
  • Frame rate and power consumption adjustable to meet system power requirements.
Signal Aggregation De-AggregationExpand Image

Single Wire aggregation

  • Aggregate multiple interfaces over one single data wire.
  • Single wire speed of up to 7.5 Mbps.
  • Robust protocol with error detection and retry features.
iCE40 UltraPlus 8 to1 Microphone Aggregation Block diagramExpand Image

8:1 Microphone Aggregation

  • Aggregate 8 PDM microphones and connection to a processor over I2S or SPI.
  • Enables use of multiple microphone for beam forming in smart speakers.

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Software

Complete Design Flows, High Ease of Use

Development Kits & Boards

Our development boards & kits help streamline your design process

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Videos

UltraPlus DHI video
Expand Video

Introducing iCE40 UltraPlus

Lattice expands its mobile FPGA product family with the iCE40 UltraPlus, delivering eight times more memory (1.1 Mbit RAM), twice the digital signal processor blocks (8x DSPs), and improved I/O over previous generations. In this video, learn more about iCE40 UltraPlus capabilities, such as driving a MIPI DSI display along with integrated SRAM memory for frame buffering.

Face Detection Using iCE40 UltraPlus
Expand Video

Human Face Detection Demo

Learn how iCE40 UltraPlus can help you with the implementation of human face detection using a neural network.

Awards

iCE40 UltraPlus Wins Editor's Choice Award for Most Competitive FPGA ProductExpand Image

China Electronic Market 2016 Editor's Choice Awards

Most Competitive FPGA Product

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
iCE40 UltraPlus Family Data Sheet
FPGA-DS-02008 2.3 10/31/2023 PDF 1.3 MB
iCE40UP WLCSP30 Pin Migration
1.1 3/16/2018 XLSX 16.4 KB
iCE40UP3K Pinout
1.1 3/16/2018 XLSX 16.1 KB
iCE40UP5K Pinout
1.1 7/8/2017 XLSX 15.6 KB
iCE40 Ultra & UltraPlus SG48 Pin Migration
2.0 10/20/2020 XLSX 15.3 KB
Package Diagrams
FPGA-DS-02053 8.2 9/22/2024 PDF 9 MB
Memory Usage Guide for iCE40 Devices
FPGA-TN-02002 1.7 10/14/2020 PDF 954.3 KB
iCE40 I2C and SPI Hardened IP - Usage Guide
FPGA-TN-02010 1.8 11/1/2022 PDF 952 KB
iCE40 SPRAM Usage Guide
FPGA-TN-02022 1.3 4/16/2021 PDF 912.9 KB
iCE40 Hardware Checklist
FPGA-TN-02006 2.3 4/18/2024 PDF 620.9 KB
iCE40 Oscillator User Guide
FPGA-TN-02008 1.8 4/12/2023 PDF 443.1 KB
iCE40 sysCLOCK PLL Design and User Guide
FPGA-TN-02052 1.4 4/30/2022 PDF 1.3 MB
iCE40 LED Driver User Guide
FPGA-TN-02021 1.5 11/29/2021 PDF 2 MB
iCE40 Programming and Configuration
FPGA-TN-02001 3.4 12/31/2022 PDF 1.8 MB
DSP Function Usage Guide for ICE40 Devices
FPGA-TN-02007 1.2 12/15/2020 PDF 947.4 KB
Advanced iCE40 I2C and SPI Hardened IP User Guide
FPGA-TN-02011 1.7 10/30/2021 PDF 1.9 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 4.9 9/23/2024 PDF 878.5 KB
Thermal Management
FPGA-TN-02044 5.2 8/21/2024 PDF 756 KB
iCE40 Technology Library
FPGA-TN-02026 3.3 9/22/2024 PDF 2.7 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.4 8/27/2024 PDF 6.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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iCE40 UltraPlus Family Data Sheet
FPGA-DS-02008 2.3 10/31/2023 PDF 1.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Migrating Designs from AMD CPLD/FPGA Devices to Lattice FPGA Devices
FPGA-AN-02081 1.1 8/27/2024 PDF 2.6 MB
Memory Usage Guide for iCE40 Devices
FPGA-TN-02002 1.7 10/14/2020 PDF 954.3 KB
iCE40 I2C and SPI Hardened IP - Usage Guide
FPGA-TN-02010 1.8 11/1/2022 PDF 952 KB
iCE40 SPRAM Usage Guide
FPGA-TN-02022 1.3 4/16/2021 PDF 912.9 KB
iCE40 Hardware Checklist
FPGA-TN-02006 2.3 4/18/2024 PDF 620.9 KB
iCE40 Oscillator User Guide
FPGA-TN-02008 1.8 4/12/2023 PDF 443.1 KB
iCE40 sysCLOCK PLL Design and User Guide
FPGA-TN-02052 1.4 4/30/2022 PDF 1.3 MB
iCE40 LED Driver User Guide
FPGA-TN-02021 1.5 11/29/2021 PDF 2 MB
iCE40 Programming and Configuration
FPGA-TN-02001 3.4 12/31/2022 PDF 1.8 MB
DSP Function Usage Guide for ICE40 Devices
FPGA-TN-02007 1.2 12/15/2020 PDF 947.4 KB
Advanced iCE40 I2C and SPI Hardened IP User Guide
FPGA-TN-02011 1.7 10/30/2021 PDF 1.9 MB
Solder Reflow Guide for Surface Mount Devices
FPGA-TN-02041 4.9 9/23/2024 PDF 878.5 KB
Thermal Management
FPGA-TN-02044 5.2 8/21/2024 PDF 756 KB
PCB Layout Recommendations for BGA Packages
FPGA-TN-02024 5.4 8/27/2024 PDF 6.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
iCE40UP WLCSP30 Pin Migration
1.1 3/16/2018 XLSX 16.4 KB
iCE40UP3K Pinout
1.1 3/16/2018 XLSX 16.1 KB
iCE40UP5K Pinout
1.1 7/8/2017 XLSX 15.6 KB
iCE40 Ultra & UltraPlus SG48 Pin Migration
2.0 10/20/2020 XLSX 15.3 KB
Package Diagrams
FPGA-DS-02053 8.2 9/22/2024 PDF 9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
iCE40 Technology Library
FPGA-TN-02026 3.3 9/22/2024 PDF 2.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
iCE40 Ultra Self-Learning IR Remote Design Files
UG74 1.0 7/15/2014 ZIP 5.8 MB
Sensor Interface and Preprocessing Reference Design - Documentation
FPGA-RD-02048 1.3 9/26/2018 PDF 1.4 MB
iCE40 Ultra Barcode Emulation User’s Guide
UG73 1.0 7/15/2014 PDF 4.3 MB
iCE40 Ultra Barcode Emulation Design Files
UG73 1.0 7/15/2014 ZIP 5.9 MB
Sensor Interfacing and Preprocessing Reference Design - Source Code
1.3 9/26/2018 ZIP 1.4 MB
iCE40 Ultra Self-Learning IR Remote User’s Guide
UG74 1.0 7/15/2014 PDF 2.9 MB
iCE40 Ultra RGB LED Controller Design Files
1.0 7/15/2014 ZIP 9.2 MB
iCE40 Ultra RGB LED Controller User Guide
UG75 1.0 7/15/2014 PDF 2.9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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PCN12A-16 KYEC Alternate Qualified Test Site
Test Site 		PCN12A-16 1.0 8/25/2016 PDF 184.7 KB
PCN09A-19 BOM comparison final
2.0 1/8/2020 XLSX 24.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs. 		FPGA-SC-02005 8.2 8/8/2024 ZIP 2.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Product Selector Guide
I0211 46.0 7/18/2024 PDF 9.7 MB
iCE40 UltraPlus Product Brochure
I0255 3.0 4/9/2019 PDF 960.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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SN_SG48
Rev C1 9/20/2019 PDF 52.9 KB
UWG30
Rev B 4/19/2018 PDF 22.7 KB
iCE40 FPGA Product Family Qualification Summary
Rev U 3/25/2021 PDF 1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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The Industry Case for Distributed Heterogeneous Processing
WP0008 1.0 12/12/2016 PDF 641.9 KB
IoT Sensor Connectivity and Processing with Ultra-Low Power, Small Form-Factor FPGAs
1.0 4/3/2018 PDF 3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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iCE40 UltraPlus IBIS Model
2.0 1/16/2018 IBS 939.6 KB

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