iCE40 UltraPlus – ML/AI Low Power FPGA

Low power, edge intelligent FPGA. Lowest power machine learning solution with flexible interfaces.

Low Power Connectivity and Computing – With the rising complexity of systems used to power smart homes, factories and cities, the iCE40 UltraPlus FPGA can solve connectivity issues with a wide variety of interfaces and protocols and provide the low power computational resources for higher levels of intelligence.

Edge Intelligent FPGA – The iCE40 UltraPlus FPGA with 5k lookup tables (LUTs) is able to implement Neural Networks for pattern matching necessary to bring always-on intelligence to the edge. Optimized for best-in-class power, designers can eliminate latency associated with cloud intelligence while keeping the overall system solution cost low.

Flexible Package Options – Multiple package are available to fit a wide range of applications needs. From an ultra-small 2.15 x 2.50 mm WLCSP package optimized for consumer and IoT devices, to a 0.5 mm pitch 7 x 7 mm QFN for cost optimized applications.

Features

  • Flexible logic architecture with 2800 or 5280 4 input LUTs, customizable I/O, up to 80 kbits of embedded dual port memory and 1 Mbit of embedded single port memory
  • Ultra-low power advanced process with static current as low as 75 uA and 1-10 mA active current for most applications
  • High performance signal processing using DSP blocks with multiply and accumulate functions
  • Soft Neural Network IPs and compiler for flexible Machine Learning/AI implementation
  • FPGA design tools, demos and reference designs to kick start designs
ACE 2017 Finalist Award 

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iCE40 UltraPLus Device Selection Guide
Parameter UP3K UP5K
Density LUTs 2800 5280
NVCM Yes Yes
Static Current (uA)
75 75
EBR RAM (kbits) 80 120
SPRAM (kbits) 1024 1024
PLL 1 1
I2C Core 2 2
SPI Core 2 2
Oscillator (10 kHz) 1 1
Oscillator (48 MHz) 1 1
24 mA Drive 3 3
500 mA Drive - -
16 x 16 Multiply & 32 bit Accumulator Blocks 4 8
PWM Yes Yes
0.4 mm Spacing Total I/O + Dedicated Inputs1,2
  UP3K UP5K
30-ball WLCSP (2.15 x 2.55 mm) 21 21
0.5 mm Spacing Total I/O + Dedicated Inputs1,2
  UP3K UP5K
48-pin QFN (7 x 7 mm) - 39

1. Total I/O include Dedicated I/O
2. Dedicated I/O are defined to be pins that are dedicated and cannot be used by user logic after configuration

Example Solutions

Create differentiated products by using Lattice IPs and Reference Designs.

Click Here For More IP and Reference Designs

Binarized Neural Network (BNN) Accelerator IP

  • Take advantage of the FPGA’s parallel processing capability to implement machine learning algorithms.
  • Enables implementation of BNNs that have power consumption in the mW range.

Key Phrase Detection – Lattice SensAI

  • Enable systems to always search for key phrases using a digital microphone input.
  • Consumes less than 1 mW of average power.

Human Face Detection

  • Enable artificial intelligence with an always-on image sensor, while consuming less than 1 mW of active power.
  • Frame rate and power consumption adjustable to meet system power requirements.

Single Wire aggregation

  • Aggregate multiple interfaces over one single data wire.
  • Single wire speed of up to 7.5 Mbps.
  • Robust protocol with error detection and retry features.

8:1 Microphone Aggregation

  • Aggregate 8 PDM microphones and connection to a processor over I2S or SPI.
  • Enables use of multiple microphone for beam forming in smart speakers.

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Software

Complete Design Flows, High Ease of Use

Development Kits & Boards

Our development boards & kits help streamline your design process

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Videos

UltraPlus DHI videoExpand Image

Introducing iCE40 UltraPlus

Lattice expands its mobile FPGA product family with the iCE40 UltraPlus, delivering eight times more memory (1.1 Mbit RAM), twice the digital signal processor blocks (8x DSPs), and improved I/O over previous generations. In this video, learn more about iCE40 UltraPlus capabilities, such as driving a MIPI DSI display along with integrated SRAM memory for frame buffering.

Face Detection Using iCE40 UltraPlusExpand Image

Human Face Detection Demo

Learn how iCE40 UltraPlus can help you with the implementation of human face detection using a neural network.

Awards

China Electronic Market 2016 Editor's Choice Awards

Most Competitive FPGA Product

Documentation

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