Answer Database

Diamond: Timing: Why does the hold analysis use a different speed grade?

941

All FPGA

Implementation

Timing Analysis

Diamond: Timing: Why are there two trace reports in the Lattice software?

940

All Devices

Implementation

Timing Analysis

Diamond: I/O: Can I emulate open drain IOs in simulations?

947

All Devices

Simulation

Aldec

What is the difference between an ispGAL and a GAL device?

949

GAL/ispGAL

Architecture

Configuration/Programming

How do I use the ispMach4000 global clocks?

943

ispMACH 4000

Architecture

PLL/DLL/Clock Routing

ispVM: Where is the location of old versions of ispVM System on Lattice web site?

948

All Devices

Device Programming

ispVM System

What is the state of Flip Flop outputs at power-up if the reset pins of my design registers are tied…

975

All FPGA

Architecture

General Logic

LatticeECP2/M: How do I implement edge clock routing from a Primary IO (PIO) in a LatticeECP2/M…

970

LatticeECP2/M

Architecture

PLL/DLL/Clock Routing

In LatticeSC/M IPexpress GUI for System Bus, why is the usr_clk input absent when MPI is enabled?

977

LatticeSC/M

Architecture

Configuration/Programming

ispVM: How does user check the Lattice devices supported by ispVM Embedded?

973

All FPGA

Device Programming

ispVM Embedded

ispVM: How does ispVM tool control the TCK duty cycle and/or frequency?

974

All FPGA

Device Programming

Diamond Programmer

LatticeECP3: How is the FIXEDDELAY attribute used and implemented in Single Data Rate (SDR) mode in…

972

LatticeECP3

Architecture

IO

For LatticeSC/M, when do I select "User Master Sync to Systembus Clock" in the System Bus IPexpress…

976

LatticeSC/M

Architecture

Configuration/Programming

Diamond: Place and Route: Timing: What is Auto hold-time correction setting in PAR?

929

All FPGA

Implementation

PAR

How can I determine what clock resources are being used?

928

All FPGA

Architecture

PLL/DLL/Clock Routing

How to determine lead free package option for Lattice FPGA device?

921

All Devices

Reliability and Materials

Device Materials

What is the composition of Lattice device pin?

922

All Devices

Reliability and Materials

Device Materials

Diamond: ECP2: How many generic routing signals can be used as primary clocks in a LatticeECP2/M…

908

LatticeECP2/M

Implementation

PAR

Diamond: How is the configuration file (.txt) generated by IPExpress being used?

906

All FPGA

Implementation

IPexpress

ispLEVER: Diamond: Place and Route: Suggestions and tips to place and route on a congested design?

900

All FPGA

Implementation

PAR