Answer Database

Have a question? We've got the answer.

Narrow Your Results


Search within results

Family
Category
Type of Issue
Related To
  • Topic
    ID
    Family
    Category
    Related To
  • What is the difference between a .bit file and a .jed file?
    617
    All Devices
    Other
  • Why does the following error occur: "ERROR - Environment variable 'TEMP' is set to a non-writable…
    492
    All FPGA
    Other
  • I configure a Lattice ECP2/M device with an Atmel SPI Flash. Supposedly the CCLK should run 120…
    424
    LatticeECP2/M
    Architecture
  • The LatticeXP2 device does not have a sub-LVDS input type, can I still receive sub-LVDS output…
    881
    LatticeXP2
  • The XP2 device does not have a mini-LVDS output type, can I still drive mini-LVDS inputs with the…
    879
    LatticeXP2
  • Should I add external series resistors to my parallel bus to improve the signal integrity?
    852
    All Devices
  • Why can't I drive a long PCB trace with a low current setting and get good signal quality?
    850
    All Devices
  • Should I add a series inductor between my voltage regulator output and VCC core?
    848
    All Devices
  • My device has a 3.3v VCCIO, can the device IO drive an LED directly?
    840
    All Devices
  • In PCI Express x4 core v3.3, when do we need to set VCO auto-band options in the auto-configure text…
    1062
    LatticeECP2/M
  • I have a 3-stage shift register, the software always implement it in a dual-port RAM, how can I…
    1060
    All FPGA
  • Why do I get a Reveal Logic Analyzer error 'Cannot detect JTagHub in device 0'? I'm using USB…
    1058
    All Devices
  • Why do I receive notices that my evaluation version of Aldec is about to expire. I upgraded to…
    1053
    All Devices
  • Is there a recommended way of choosing AES (Advanced Encryption Standard) encryption key?
    1644
    LatticeECP3
    Device Programming
  • How can the default/recent projects (.xcf) be cleared in the File menu of ispVM?
    1318
    All Devices
  • Why is a DRC error generated associated with the PCI Core signal/pin serrn (SERR#)?
    1315
    All Devices
  • How many DDR memory interfaces can be implemented on a single part?
    1076
    All FPGA
  • Why am I not able to update the Configuration Flash of the MachXO2 in transparent mode using the svf…
    3766
    MachXO2
    Device Programming
    Deployment Tool
  • Why did the iCEstick board get damaged while loading a bitmap to iCEstick's FLASH memory? and how to…
    3755
    iCE40
    Lattice Evaluation Board
  • Are there any limitations of using 5 V tolerant inputs on the ispMACH4000 device?
    3753
    ispMACH 4000
    Architecture
    IO
    • Page 1 of 121
    First Previous
    1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
    		Next Last
    Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.

    About Us

    Sales

    Support

     
     
     
     
     
     
    Lattice QR code