If you choose not to to sync UMI to System Bus, then all transfers between usr_clk (HCLK) and umi_clk clocks will be handled asynchronously.
So you can provide either the same or different clock sources to umi_clk and usr_clk.
If you choose to sync UMI to System Bus, then you have to make sure that the sync_clk output of the system bus is driving the umi_clk port on systembus and all the UMI logic in your design because you need to have zero phase shift between sync_clk and umi_clk in UMI sync mode.
This means that usr_clk and umi_clk will not have the same clock source in this mode.
Please refer to "Synchronous/Asynchronous Mode" section of "LatticeSC MPI/System Bus" (TN1085) for more information.