What is the state of Flip Flop outputs at power-up if the reset pins of my design registers are tied to neither GSR nor LSR?
Even if you do not use the GSR/LSR logic in RTL, GSR is always used during bitstream download. During bitstream download all flip flops are held at reset until the download is completed. So, the state of a register's Q output is always '0' or LOW at powerup.