LatticeECP2/M: How do I implement edge clock routing from a Primary IO (PIO) in a LatticeECP2/M device?
You need to locate an input buffer in a dedicated site that supports direct access to the edge clock spine.
This applies to PIOs that clock special elements like IDDR/ODDR as well as CLKDIV blocks. Typically, you need to specifiy an EDGE preference on the input buffer clock output:
USE EDGE NET "clkin" ;
If the input buffer is not at an edge clock dedicated location, then the following warning will show in PAR (example with LFE2M50E-5F484C device and IO buffer located at N21 location):
WARNING - par: Edge clock signal "clkin" -- its PIO driver comp "clkinbuf" is placed on site "N21 / PR54A": there will be no direct connection to the edge clock resources, so general routing has to be used. Instead, you should locate the clkinbuf buffer at a dedicated site for eclk routing. For the example above, H21 and J21 are such sites. This will result in the input clock net connecting cleanly to one edge clock spine.