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ID: 939
实例类型: faq
分类: Implementation
相关: Timing Analysis
产品系列: All FPGA

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Lattice Diamond: How can I block clock transfers in the timing analysis tool?

A clock domain transfer or crossing occurs when one register in a data path is clocked by CLKA and one register by CLKB.

To block this transfer from the timing analysis use the preference:
BLOCK INTERCLOCKDOMAIN

If you are looking to relax or analyze this path use the preference:
MULTICYCLE FROM CLKNET "CLKA" TO CLKNET "CLKB" 2 X ;

For more information and a complete description on these preferences refer to the ispLEVER Online Help