LatticeXP2 : What types of issues could cause the PLL to lose lock?
Situation: A CLKI input frequency to a PLL in a Lattice device is within the normal range for proper PLL operation, yet the PLL loses lock every now and then.
Answer: As an example when using a LatticeXP2 device, check that the CLK signal that arrives at the PLL input pin meets the CLKI input specifications as given in the LatticeXP2 datasheet.
TIPJIT period jitter should be less than +/-200ps rise/fall times should be less than 1ns.
Those two specifications could be violated if the CLKI signal is being passed through a low pass filter network, or if the CLKI input is also passed on to other receivers on the PCB (the additional receiver loads can cause "runt" edges). If you have concerns about edge speeds for the clock inputs the PCB, an IBIS simulation can help answer how the clock edges will look at the CLKI input.
Also check the clock source itself, does it have low jitter and a fast edge output. If not, you might look at adding a clock driver IC such as the Lattice ispClock devices. The ispClock devices provide multiple high quality low jitter clock with internal source termination. You can read more about the ispClock devices here http://www.latticesemi.com/products/ispclock/index.cfm?