Description:
RISC-V SM(v1.5)/MC(v2.5) CPUs currently only support trap handler for read access error.
- When CPU read from an invalid instruction/data address range, it will cause an exception which trigger the trap handler.
- However, if CPU write to an invalid data address range which trigger a write bus error, it is non-blocking and will not trigger write exception trap handler.
Solution:
This is a known limitation. It is recommended for user to ensure RISC-V software implementation does not access invalid addresses which doesn't exist in the SoC system.