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ID: 7234
实例类型: faq
分类: PCIe
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产品系列: CertusPro-NX

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PCIe for Nexus FPGAs: Why is PCIe IP downgraded to x1 lane even though it is configured as x1 lane?

Description:
This is a potential bug in the GUI setup

Solution:
To workaround the issue, use LMMI to write '1' (configured to max width x1) on bit [18:16] of register 0x20.


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