PCIe for Nexus FPGAs: What is the size of the Transmit Buffer and Receive Buffer in PCIe X1 IP Core and PCIe X4 IP Core?
The Transmit Buffer and Receive Buffer size is 2 kByte each.
These RAM buffer sizes are fixed because it is a Core internal RAM, so the negotiated Maximum Payload Size (MPS) size will determine how many TLPs can be stored.
For instance, in the Receive Buffer, if MPS is low, more TLPs can be stored, if MPS is at maximum (512 bytes) fewer TLPs can be stored.