Solution:
If the debug is enabled, it is synchronous. If not, then it is controlled by an input reset (either synchronous or asynchronous) and by watchdog timer (synchronous). This is valid for the RISC-V RX.
Unfortunately RISC-V MC and SM does not have an integrated watchdog timer. With that, the reset output is retimed when the debug module is present and is a passthrough of the reset input otherwise.