What is the spec of 'sync_clk_i' of MIPI D-PHY Rx IP? Does the signal require to be in synced with any other clocks?
Description:
Spec is given that 'sync_clk_i', or the 'Sync clock frequency', can support 24-200Mhz, and it is defaulted to 60Mhz, based on CSI-2/DSI D-PHY Rx IP Core IPUG 02081 document.
'syn_clk_i' does not need to synchronize with any clocks, and should be treated as a startup clock which is standalone.
In Soft D-PHY mode, 'syn_clk_i' drives the GDDR_SYNC cell, which supplies the STOP signal to the ECLKSYNC. This signal gates the ECLKSYNC output, and effectively the ECLKDIV output, so 'syn_clk_i' cannot possibly be any clock derived from the ECLKDIV.
This is based on the information from CrossLink-NX HighSpeed IO Interface technical note document (FPGA-TN-02097), Chapter 5.10.1, Figure 5.19 & Table 9.3.