Description:
This is encountered if the signal is being defined (for example in a constraint file) and that signal is optimized (or the net does not exist in the design) by the synthesis tool. To fix the error, add the following attribute to the signal.
Solution:
To work around this issue, assuming the net exists from the RTL design, use a synthesis attribute shown below to prevent the tool from optimizing the net from both Synthesis and Map perspectives.
/*synthesis syn_keep=1 NOMERGE = "ON" */;
Alternatively, you can check if the signal name has been changed or altered in the design. For example, from SCLK_IN to SCLK_IN_c. If this applies, then simply change the constraint to the correct entity.