If you are not using the PLL or don't know whether you will be using the PLL, then I recommend that you connect the external clock to the PCLK pin. It can still be routed to the PLL by the software if necessary.
The PCLK pin provides the shortest path and hence the least delay for a clock signal getting to the primary clock routing resources in the FPGA. This is why this is the preferred pin to use for a primary clock.
The PCLK pin will have a longer path and hence a greater delay in getting to the PLL than if you use the PLL_T (preferred) or PLL_C pin. However, you may be able to use the PLL phase shift feature to compensate for this greater delay if it becomes a problem for your design. Usually the increased delay is less important for a PLL signal than for a primary clock signal.