All FPGA: Why are the power rails for DDR3_VTT and VCC_1V5 connected to one another?
The DDR3 VCC_1V5 powers the DDR3 and the DDR3_VTT is the data buss termination, by using de-caps from DDR_VTT to gnd and VCC_1V5 the data buss is stabilized and centered between the power rails for better signal integrity for all data patterns.