Description:
Auto computation of FIFO Depth and FIFO Delay attributes does not consider for the pad codes inserted in the packet data. The current setting may cause FIFO Empty and FIFO Full states if pad codes are present in the packet data.
Adjust manually to avoid FIFO Empty or FIFO Full states during packet transfer.
Pad codes are not considered in the default FIFO setting computations. FIFO computation formulas can be found on page-11 of SLVS-EC Receiver IP User Guide (FPGA-IPUG-02125).
Please check if you have properly set the FIFO settings when they added pad codes.
If there are pad codes, add them to the Byte Count, and re-compute for new FIFO DELAY/DEPTH (i.e. byte count is 12288 and additional 1200 bytes of pad codes per line, new byte count = 12288 + 1200 = 13488).