ispLEVER Classic: OCSTIMER (On Chip OSC) sample Verilog code has an issue with the RTL simulation using ModelSim
Description:
There is a typo error on the ispLEVER Classic OSCTIMER sample Verilog code.
Solution:
Please change the small letter to an upper case. Please note that Verilog is a case-sensitive language and differences in incorrect cases will affect its functionality.
From this:
defparam I1.TIMER_DIV = "128";
osctimer I1 (.DYNOSCDIS(DYNO), .TIMERRES(RST),
.OSCOUT(CLK_5MHZ), .TIMEROUT(DIV_CLK));
To this:
defparam I1.TIMER_DIV = "128";
OSCTIMER I1 (.DYNOSCDIS(DYNO), .TIMERRES(RST),
.OSCOUT(CLK_5MHZ), .TIMEROUT(DIV_CLK));
Note that there is no plan to update this.