Solution:
One bit asserted and flag as 1. FEA OTP has been asserted which means that feature row is set to be one-time programmable. The expected value should be unasserted which is 0; however, it got an error because this bit (error 15) asserted to 1.
You may check with FPGA-TN-02039 (page 9) that shares the same table for 32-bit Status Register with Crosslink although the document is referred as ECP5 and ECP5-5G sysCONFIG Usage Guide.