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ID: 3981
实例类型: faq
分类: Simulation
相关: Aldec
产品系列: All FPGA

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Active-HDL: How to resolve unknowns (X) in timing simulation when the RTL simulation is fine and all constraints are met in Place and Route TRACE?

For post-route timing
simulation, please set the SDF (Standard Delay Format) value and load as Maximal and Yes,
respectively, in Aldec design settings.

i.e.
Step 1: In Aldec Active-HDL,
select "Settings" from the Design menu. The Design Settings dialog box
will be displayed. Expand the Simulation category and select the SDF
subcategory.
Step 2: In the SDF tab, set the SDF value and load as Maximal and Yes, respectively. (see the attached image file)
Step 3: Select Compile All from the Design menu.
Step 4: Select Initialize Simulation from the Simulation menu.

Now, select Simulation >> Run to see the waveforms.


Also, check if the SDF needs a fixed simulation resolution timing setting of say, 1ps.