LatticeECP2/M/ECP3/ECP5/ECP5-5G: Can we disable the Reset Signal for RAM_DQ, RAM_DP and RAM_DP_TRUE in our design?
The reset signals for the Embedded Block RAM (EBR) based RAM_DQ, RAM_DP, and RAM-DP_TRUE reset only the output registers, not the EBR memory contents.
So, if you do not want to reset the output registers of these modules in your design, you can disable them.