Out of 1000 interrupts, approximately 300 reaches to CPU, when PCIe core's interrupt assert and de-assert gap is 8 clock duration of wb_clk.
When the IP detects that inta_n is asserted low, it needs 8 clocks to create the ASSERT_INTA packet. In case of de-assertion, inta_n should not be de-asserted immediately following the 8 cycle.
Rather, user logic should detect whether the interrupt has been serviced before de-asserting the interrupt.
Also, status of the MSI interrupts, when using inta_n (legacy) interrupt, these interrupts should be disabled.