The CDR Lock detection circuit is a digital counter based on the
reference clock. If the clock is removed while the CDR is lock, CDR
Loss of Lock will continue to indicate lock status (last registered
state).
If the input to the Receiver is removed, it will take some time for the lock detection circuit to detect unlocking assuming the reference clock is running.
The LatticeECP3 CDR loss of lock response time is listed on table 8-9 of the LatticeECP3 Serdes/PCS Usage Guide