Deployment Tool: Why is the bit count for a Serial Vector Format Verify operation greater than my BIT file?
Solution:
The number of bits shifted for a Verify operation can be larger than the bit count of the base BIT file for the FPGA. How many extra bits typically depends on the communication interface used. When using the JTAG port the bit counts will be identical. When using the Slave SPI (SSPI) port the SVF may require a few extra bits to transmit the starting address to the SPI PROM. The number of additional bits is usually very small.