All Devices: Is the PLL Lock time, Tlock, measured from power ramp up?
The lock time of the PLL is not gated to power ramp up, it is dependent on the reset signal. After the FPGA is finished configuring, a global reset signal (GSR) is asserted to the chip prior to waking up and operating. PLL lock time, Tlock, is specified from the time the GSR is released to the time of lock, as long as the input clock is consistent.