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ID: 1607
实例类型: faq
分类: Architecture
相关: SERDES/PCS
产品系列: LatticeECP3

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LatticeECP3:  What is the depth of Serdes down/up-sampling FIFOs?

The depth of Serdes down/up-sampling FIFOs is four. It is very shallow. It requires that the read and write clock to them come from the same clock source. Only phase difference between read and write clocks is allowed in order to make these FIFOs function correctly. If there is any ppm frequency difference between read and write clocks, down/up-sampling FIFOs will report error in the channel-based signals (FFS_RXFBFIFO_ERROR and FS_TXFBFIFO_ERROR).