The MachXO2 family, in 1200 LUT and higher densities, have an Edge Clock Bridge that is used to route clock sources onto the Edge Clocks resources in the device.
The bridge allows either a primary clock input, or a PLL clock to be routed to the Edge Clock routing on the top and bottom of the device. The Edge Clock Bridge routes the clock to the edge of the device with very little skew.
For a description of the Edge Clock Bridge please see the MachXO2 sysClock PLL Design and Usage Guide, TN1199.