The amount of time needed to perform an SRAM CRC Error Detection check depends on the density of the MachXO2 device and the frequency of the SRAM CRC Error Detection Clock Driver signal. There will also be some overhead time for calculation, but it is fairly short in comparison. An approximation of the time required can be found by using the following formula:
(Maxbits/8)/ SRAM CRC Error Detection Clock Driver Frequency=Time(ms)
Maxbits is in KBits and depends on the density of the MachXO2 device. The SRAM CRC Error Detection Clock Driver signal frequency is shown in MHz. Time is in milliseconds. The SRAM CRC Error Detection checking in the MachXO2 device reads 8 bits(1 byte) on each SRAM CRC Error Detection clock cycle.
For example, for a design using MachXO2 with 4,000 look-up tables and an SRAM CRC Error Detection Clock Driver frquency of 7 MHz:
(972KBits/8) /7.0MHz=17.4ms
For more details of SED, please refer to MachXO2 SRAM CRC Error Detection Usage Guide.