FAQ

My current design under simulation is in VHDL which uses a Verilog module (Lattice Tri-speed MAC) in which a ipExpress generated PLL (another Verilog module) is used. The ipExpress generated Verilog module contains several defparam specifications to set the EHXPLLA parameters. Using Active-HDL (ispLever 7.1) the Verilog compiles without problems. But during elaboration before the simulation starts I get a fatal error: ELAB2: Fatal Error: ELAB2_0093 The defparam statement from module "rxmac_clk_pll" in "/TSMAC/U1_rxmac_clk_pll" points to variable "SMI_OFFSET" in a non-Verilog design region "/TSMAC/U1_rxmac_clk_pll/rxmac_clk_pll_0_0". What is wrong here, and how can this be fixed?

Assuming that the design is targeted to SC/SCM and the top level is VHDL that instantiates a PLL in Verilog.

ovi_sc is the Verilog library and sc is the library for VHDL.

If  -L sc is being used, the PLL will try to match a Verilog parameter to a VHDL generic at the top level and they may be incompatible. Hence using -L ovi_sc instead, will help to get rid of the error message.