What is the clock frequency of the rx_full_clk_ch# from the SERDES PCS when there is no valid data being received?
The rx_full_clk_ch# output from the SERDES PCS maintains its relationship to the SERDES reference clock (refclk) so long as the Clock and Data Recovery (CDR) circuit maintains a lock condition. Without valid data arriving the CDR is not guaranteed to stay locked. The rx_full_clk_ch# output is indeterminate when the CDR loses lock. You should not use the rx_full_clk_ch# output as a clock source if incoming data is not guaranteed to be valid and continuous.