POS PHY Level 3链路

Edge AI Accelerated Object Detection On FPGA

LatticeReferenceDesign-LogoPOS PHY Level 3规范定义了物理层(PHY)设备和链路层设备的互连,实现了Packet over SONET(POS)。POS PHY Level 3接口涵盖了所有应用,比特率高达2.4 Gbit/s。该规范确定了用于链路层设备的设计特点和要求。该设计在实现了一个POS PHY Level 3链路层接口的同时,还可以用于与通用FIFO通信。它的目的是使用户应用(链路层设备)通过基于该规范的接口和通用FIFO连接。

Features

  • Identify and track several objects at once, even in dynamic or crowded scenes
  • Efficient AI models optimized for edge devices, enabling always-on operation
  • Identify and track several objects at once, even in dynamic or crowded scenes
  • Supports a wide range of object classes and deployment scenarios
  • Easily connects to existing infrastructure and legacy systems
  • Accurate detection and tracking for safety-critical and monitoring applications

Block Diagram

Multi Object Detection Reference Design

文档

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Multi Object Detection Reference Design and Demonstration Documentation
To learn more about this product design and to access the complete source code, bitstream and user guide in GitHub, please click here
1/18/2026 WEB