EP201: PowerPC 总线主控制器

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PowerPC总线主控制器是一个总线接口单元,专用于PowerPC主机总线。使用户通过一个很简单的用户接口在PowerPC CPU总线上直接进行数据传输。

在开始传输前,PowerPC总线主控制器仲裁PowerPC的地址总线。处理独立的地址和数据总线的使用权,所以可以独立地从地址总线中仲裁数据总线。通过CPU总线上的CPU或其他资源,该总线主控制器处理地址重试。根据地址重试,会自动重新启动数据传输,除非发生了错误。

支持单拍,突发数据和扩展MPC8260数据传输。允许不同大小的数据和传输类型,并且可以通过内部的后端总线来指定。由总线主控制器提供两个用户接口端口。通过单总线主控制器,允许两个不同的器件访问PowerPC总线。总线主控制器包含两个请求端口之间进行仲裁的仲裁逻辑。

Features

  • Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
  • Automatic bus arbitration for address bus and data bus based on internal bus request.
  • Separate address bus and data bus tenure with individual grant signals.
  • Supports address bus retry and data transfer error.
  • Qualified address bus grant and data bus grant through the use of bus busy signals.
  • User specified burst data transfer and single beat data transfer.
  • Supports two back-end user request ports with built-in arbitration.
  • Efficient back-end bus for internal data transfer.
  • Supports bus parking.
  • Designed for ASIC or programmable logic device implementations in various system environments.
  • Fully static design with edge triggered flip-flops.
  • Optimized for ispXPGA product family.

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Block Diagram

性能和大小

以下是典型的性能和利用率的结果。

器件 利用率 性能
PFUs Slices LUTs 百分比
LFX1200B 133 4% 94Mhz
LFFC20 527 4% 115Mhz
LFXP10 431 8% 115Mhz
LFXP2-17E 298 4% 143Mhz

Ordering Information

This IP core is supported and sold by Eureka Technology, contact Eureka Technology at info@eurekatech.com or visit their website at www.eurekatech.com for more information.

文档

快速参考
标题 编号 版本 日期 格式 文件大小
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PowerPC Bus Master Datasheet
EP201 6/22/2007 PDF 91.6 KB