DDR3 Memory Interface Demonstration

800 Mbps Data Manipulation

The DDR3 Demo Design consists of two major parts: the DDR3 SDRAM Controller IP core and the User Logic block. The DDR3 SDRAM Controller IP core interfaces directly with the onboard external DDR3 SDRAM to perform control, write, and read operations. The User Logic block generates test data to be written to the SDRAM and compares the data read from the external DDR3 SDRAM to the expected result, flagging an error if a data mismatch is detected. The demo parameters can be modified using onboard DIP switches, whereas the status of the demo is indicated through the onboard LEDs.

This demo uses Certus-NX Versa Evaluation Board that can expand the usability of the Certus-NX FPGA with DDR3, soft D-PHY, 1 Gbps Ethernet and 1× PCIe (Gen2) channel. Board resources such as jumpers, LED indicators, push buttons, and switches are available for user-defined applications.

Lattice DDR3 SDRAM Controller IP - This demo design demonstrates the functionality of the Lattice DDR3 SDRAM Controller IP operating at a core speed of 400 MHz and 800 Mbps.

DDR3 Demo - Allows you to manipulate test patterns and observe the results through onboard LEDs.

State Machine Generation - Allows you to control certain parameters through DIP switches to modify demo test patterns.

Running Reveal Analyzer - Allows you to observe critical signals through Reveal Analyzer


  • Generates 16-bit test data
  • Writes to the onboard DDR3 SDRAM
  • Reads the DDR3 SDRAM and compares the data with the original expected data
  • Allows you to initiate resets to the DDR3 SDRAM Controller and user logic

Block Diagram


标题 编号 版本 日期 格式 文件大小
DDR3 Demo on Certus-NX Versa Evaluation Board User Guide
FPGA-UG-02148 1.0 2/23/2022 PDF 1 MB
标题 编号 版本 日期 格式 文件大小
DDR3 Demo on Certus-NX Versa Evaluation Board Bitstream
1.0 2/23/2022 ZIP 2.4 MB
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