AXI Register Slice IP Core

Direct and Fast Connection Between a Processor and High-performance Memory

The AXI Register Slice core connects one AXI standard manager to one AXI standard subordinate by introducing pipeline stages in between the two to close timing in critical paths. Different configuration options are available. Each AXI channel transfers information in only one direction and the architecture does not require a fixed relationship between the channels. The user can insert a register slice at almost any point in any channel, with an additional cycle of latency.

Uses Simple Register Slices for a Direct and Fast Connection – This IP core allows direct, fast connection between a processor and high-performance memory, by using simple register slices to isolate the longer path to less performance critical peripherals.

Latency Cycles and Maximum Operation Frequency Trade-Off – This IP core also allows trade-off between cycles of latency and the maximum frequency of operation.

Features

  • Individually configurable AXI channels.
  • One latency cycle per register-slice by default.
  • Support for AXI3, AXI4, and AXI4-Lite modes of the AXI protocol.
  • Full-Weight, Light-Weight, and Input Registered modes of operation.
  • Ability to facilitate timing closure by trading-off frequency versus latency.

Block Diagram

Resource Utilization

LAV-AT-500E
Bus Mode Registers LUTs EBRs Synthesis Tools
AXI4 Full-Weight 441 247 0 Synplify Pro 2022.1
AXI4 Light-Weight 226 20 0 Synplify Pro 2022.1
AXI4 Input Registered 998 635 0 Synplify Pro 2022.1
AXI3 Full-Weight 390 220 0 Synplify Pro 2022.1
AXI3 Light-Weight 197 435 0 Synplify Pro 2022.1
AXI3 Input Registered 876 558 0 Synplify Pro 2022.1
AXI4-Lite Full-Weight 306 185 0 Synplify Pro 2022.1
AXI4-Lite Light-Weight 152 21 0 Synplify Pro 2022.1
AXI4-Lite Input Registered 675 739 0 Synplify Pro 2022.1

NOTE: Target Device for all is LAVAT500E-1LFG676I

LFCPNX-100
Bus Mode Registers LUTs EBRs Synthesis Tools
AXI4 Full-Weight 444 247 0 Synplify Pro 2022.1
AXI4 Light-Weight 227 20 0 Synplify Pro 2022.1
AXI4 Input Registered 1121 963 0 Synplify Pro 2022.1
AXI3 Full-Weight 390 220 0 Synplify Pro 2022.1
AXI3 Light-Weight 200 20 0 Synplify Pro 2022.1
AXI3 Input Registered 986 857 0 Synplify Pro 2022.1
AXI4-Lite Full-Weight 306 185 0 Synplify Pro 2022.1
AXI4-Lite Light-Weight 152 21 0 Synplify Pro 2022.1
AXI4-Lite Input Registered 756 667 0 Synplify Pro 2022.1

NOTE: Target Device for all is LFCPNX100-7ASG256I

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
AXI Register Slice IP Core - Lattice Radiant/Propel Builder
FPGA-IPUG-02235 1.0 7/21/2023 PDF 2.3 MB

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