ispMACH 4000ZE

Ultra low power, high performance

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High performance, maximum flexibility – The ispMACH4000ZE family integrates up to 256 macrocells that support individual clock reset, preset and clock enable controls that operate at frequencies of up to 260 MHz.

Guard against power drain – Reduce dynamic power consumption to as low as 10 μA by using Power Guard to selectively disable inputs. Reduce system power with per pin pull-up, pull-down or bus keeper control.

Simplify system integration – With flexible multi-volt IOs that support LVCMOS 3.3, LVTTL and PCI and multiple temperature range support, integration into both commercial and industrial designs couldn’t be easier.

Features

  • Ultra low power with standby current as low as 10 μA
  • 5 V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
  • JTAG In-System Programmable (ISP™)
  • Available in TQFP, csBGA and ucBGA packages
  • Multiple temperature range support: Commercial 0 to 90°C junction (Tj), Industrial -40 to 105°C junction (Tj)

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ispMACH 4000ZE (1.8 V) Device Selection Guide

Parameters 4032ZE 4064ZE 4128ZE 4256ZE
Density Macrocells 32 64 128 256
tpd (ns) 4.4 4.7 5.8 5.8
tco (ns) 3.0 3.2 3.8 3.8
ts (ns) 2.2 2.5 2.9 2.9
fMAX (MHz) 260 241 200 200
Supply Voltage (V) ZE=1.8 ZE=1.8 ZE=1.8 ZE=1.8
I/O Standard Support LVTTL, LVCMOS3.3/2.5/1.8/1.5, PCI3.3
Embedded Oscillator Yes Yes Yes Yes
5 V Tolerant I/Os Yes Yes Yes Yes
Typical Standby Current (µA) 10 11 12 13
Temperature Grades C/I C/I C/I C/I
0.4 mm Spacing I/O Count + Inputs
  4032ZE 4064ZE 4128ZE 4256ZE
64 ucBGA (4 x 4 mm) 48 + 4
132 ucBGA (6 x 6 mm) 96 + 4
0.5 mm Spacing I/O Count + Inputs
  4032ZE 4064ZE 4128ZE 4256ZE
48 TQFP (7 x 7 mm) 32 + 4 32 + 4
100 TQFP (14 x 14 mm) 64 + 10 64 + 10 64 + 10
144 TQFP (20 x 20 mm) 96 + 4 96 + 14
64 csBGA (5 x 5 mm) 32 + 4 48 + 4
144 csBGA (7 x 7 mm) 64 + 10 96 + 4 108 + 4

Design Resources

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Software

Complete Design Flows, High Ease of Use

Development Kits & Boards

Our development boards & kits help streamline your design process

Programming Hardware

Take the strain out of in-system programming & in-circuit reconfiguration with our programming hardware

Documentation

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Quick Reference
Technical Resources
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Package Diagrams
FPGA-DS-02053 8.2 9/22/2024 PDF 9 MB
ispMACH 4000 Timing Model Design and Usage Guidelines
TN1004 9/1/2001 PDF 63.4 KB
ispMACH 4000ZE Timing Model Design and Usage Guidelines
TN1168 01.1 1/20/2010 PDF 108.6 KB
Using ispMACH 4000 Devices in Multiple JTAG Voltage Environments
TN1019 4/1/2002 PDF 460.1 KB
Using a Discrete Crystal as a PLD Clock Source
FPGA-AN-02016 1.1 6/21/2021 PDF 672.5 KB
USB Programming and Circuit Guide
FPGA-AN-02015 1.2 1/22/2021 PDF 1.4 MB
Using Multiple Boundary Scan Port Linker (BSCAN2)
FPGA-AN-02017 1.1 1/9/2022 PDF 774.3 KB
Advanced Features of the ispMACH 4000ZE Family
TN1174 01.1 4/29/2008 PDF 235.5 KB
Power Estimation in ispMACH 4000ZE Devices
TN1187 01.0 8/18/2008 PDF 59.9 KB
SPI Flash Programming and Hardware Source Archive
TN1081 3/2/2005 ZIP 1.8 KB
SPI Flash Programming and Hardware Interfacing Using ispVM System
TN1081 3/2/2005 PDF 685.9 KB
Power Decoupling and Bypass Filtering for Programmable Devices
FPGA-TN-02115 1.1 1/26/2022 PDF 708.9 KB
Thermal Management
FPGA-TN-02044 5.2 8/21/2024 PDF 756 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
ispMACH 4000ZE Family Data Sheet
DS1022 1.9 10/29/2015 PDF 4.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
ispMACH 4000 Timing Model Design and Usage Guidelines
TN1004 9/1/2001 PDF 63.4 KB
ispMACH 4000ZE Timing Model Design and Usage Guidelines
TN1168 01.1 1/20/2010 PDF 108.6 KB
Using ispMACH 4000 Devices in Multiple JTAG Voltage Environments
TN1019 4/1/2002 PDF 460.1 KB
Using a Discrete Crystal as a PLD Clock Source
FPGA-AN-02016 1.1 6/21/2021 PDF 672.5 KB
USB Programming and Circuit Guide
FPGA-AN-02015 1.2 1/22/2021 PDF 1.4 MB
Using Multiple Boundary Scan Port Linker (BSCAN2)
FPGA-AN-02017 1.1 1/9/2022 PDF 774.3 KB
Advanced Features of the ispMACH 4000ZE Family
TN1174 01.1 4/29/2008 PDF 235.5 KB
Power Estimation in ispMACH 4000ZE Devices
TN1187 01.0 8/18/2008 PDF 59.9 KB
SPI Flash Programming and Hardware Source Archive
TN1081 3/2/2005 ZIP 1.8 KB
SPI Flash Programming and Hardware Interfacing Using ispVM System
TN1081 3/2/2005 PDF 685.9 KB
Power Decoupling and Bypass Filtering for Programmable Devices
FPGA-TN-02115 1.1 1/26/2022 PDF 708.9 KB
Thermal Management
FPGA-TN-02044 5.2 8/21/2024 PDF 756 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Package Diagrams
FPGA-DS-02053 8.2 9/22/2024 PDF 9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
ispMACH 4256ZE Breakout Board Evaluation Kit User's Guide
EB65 01.1 3/26/2012 PDF 2.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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SPI WISHBONE Controller - Documentation
RD1044 1.7 3/1/2014 PDF 960 KB
Serial Peripheral Interface (SPI) - Documentation
RD1075 1.1 12/23/2011 PDF 158.7 KB
SPI GPIO Expander - Documentation
RD1073 1.1 12/23/2010 PDF 212.5 KB
SPI GPIO Expander - Source Code
RD1073 1.1 12/23/2010 ZIP 161.6 KB
SPI WISHBONE Controller - Source Code
RD1044 1.8 1/12/2015 ZIP 477.7 KB
Serial Peripheral Interface (SPI) - Source Code
RD1075 1.1 12/23/2011 ZIP 124.8 KB
UART (Universal Asynchronous Receiver/Transmitter) - Source Code
RD1011 1.7 1/1/2015 ZIP 766.4 KB
Wake on LAN - Source Code
RD1096 1.0 6/24/2010 ZIP 283.1 KB
Wake on LAN - Documentation
RD1096 1.0 6/24/2010 PDF 311.6 KB
GPIO Expander, Documentation
RD1065 1.3 4/12/2011 PDF 280.6 KB
HDLC Controller Implemented in ispMACH 4000ZE and CPLD Families - Source Code
RD1009 3.1 7/15/2009 ZIP 731.5 KB
GPIO Expander, Source Code
RD1065 1.3 4/12/2011 ZIP 195.5 KB
Fast Page Mode SDRAM Controller - Documentation
FPGA-RD-02090 2.4 1/22/2021 PDF 887.1 KB
Fast Page Mode SDRAM Controller - Source Code
RD1014 2.3 11/8/2010 ZIP 110.4 KB
I2C Controller for Serial EEPROMs - Documentation
RD1006 2.6 3/5/2014 PDF 767.9 KB
I2C (Inter-Integrated Circuit) Master Controller - Source Code
RD1005 5.9 1/10/2015 ZIP 809.7 KB
I2C Controller for Serial EEPROMs - Source Code
RD1006 2.7 1/12/2015 ZIP 613.5 KB
I2C (Inter-Integrated Circuit) Master Controller - Documentation
RD1005 5.8 3/6/2014 PDF 987.4 KB
HDLC Controller Implemented in ispMACH 4000ZE and CPLD Families - Documentation
Also download the source code below 		RD1009 03.1 7/1/2009 PDF 566 KB
ispMACH 4256ZE Breakout Board Evaluation Kit Source
This demo includes the ispLEVER Classic project source for the preprogrammed demonstration. It programs the LC4256ZE-TN144C with a counter circuit using the embedded oscillator timer and I/O buffers configured for LED drive. 		1.0 3/21/2011 ZIP 75.7 KB
BSCAN2 - Multiple Scan Port Linker - Documentation
FPGA-RD-02106 4.9 1/29/2021 PDF 918.1 KB
Advanced SDR SDRAM Controller - Design Documentation
FPGA-RD-02087 4.9 1/22/2021 PDF 1.1 MB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Source Code
RD1001 7.3 4/18/2011 ZIP 152.4 KB
BSCAN2 - Multiple Boundary Scan Port Linker - Source Code
RD1002 4.6 3/13/2014 ZIP 2.6 MB
BSCAN1 - Multiple Boundary Scan Port Addressable Buffer - Documentation
FPGA-RD-02105 7.4 1/29/2021 PDF 993.7 KB
Arbitration and Switching Between Bus Masters - Documentation
FPGA-RD-02104 1.2 1/21/2021 PDF 952.5 KB
Advanced SDR SDRAM Controller - Source Code
RD1010 4.8 9/12/2014 ZIP 495.7 KB
Arbitration and Switching Between Bus Masters - Source code
RD1067 1.1 2/22/2010 ZIP 284 KB
Read and Write Usercode - Source Code
RD1041 1.3 3/1/2014 ZIP 618.2 KB
PCI Target 32-bit/33MHz
FPGA-RD-02134 3.6 1/31/2021 PDF 1.8 MB
Read and Write Usercode - Documentation
RD1041 1.4 9/17/2014 PDF 831.5 KB
PWM Fan Controller
RD1060 1.6 9/10/2014 PDF 481.5 KB
LED/OLED Driver - Source code
RD1103 1.1 3/1/2014 ZIP 1.4 MB
LPC (Low Pin Count) Bus Controller - Source Code
RD1049 1.6 4/12/2011 ZIP 517.2 KB
LPC (Low Pin Count) Bus Controller Reference Design - Documentation
FPGA-RD-02114 1.7 1/21/2021 PDF 1 MB
LED/OLED Driver - Documentation
RD1103 1.1 3/1/2014 PDF 989.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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PCN05A-17 Halogen-Free substrate at ASEM
1.2 10/27/2017 PDF 268 KB
PCN05A-17 Affected Parts List
1.0 1/1/0001 XLSX 14.9 KB
PCN 09A-12 Affected Devices
Assembly Site 		PCN09A-12 1.0 5/14/2012 XLSX 121 KB
PCN 09A-12 Alternate Qualified Material Set, Assembly Site for Select Lattice Families
PCN09A-12 1.0 5/14/2012 PDF 160.2 KB
PCN 04A-12 - Revision to ispMACH 4000ZE Data Sheet
Data Sheet 		PCN04A-12 1.0 2/27/2012 PDF 50.7 KB
PCN 09A-12 Material Set Changes
Assembly Site 		PCN09A-12 1.0 5/14/2012 XLSX 121 KB
PCN 04A-12 Affected Devices List
PCN04A-12 2/24/2012 XLSX 25 KB
PCN 09A-12 Frequently Asked Questions
PCN09A-12 1.0 5/11/2012 PDF 178.9 KB
PCN03A-13 Device Characterization Report
PCN03A-13 6/28/2013 PDF 981.3 KB
PCN 03B13 Alternate Qualified Assembly Test Site Alternate Qualified Material Sets ASE Taiwan
Assembly Site, Material Set 		PCN03B 1.0 11/14/2014 PDF 229.6 KB
PCN03A-13 FAQs
PCN03A-13 6/28/2013 PDF 458.3 KB
PCN03B-13 Affected Part Number and Material Sets
PCN03B-13 6/28/2013 XLSX 69 KB
PCN08A13_AffectedDevices
Other 		PCN08A-13 1 9/26/2013 XLSX 78.2 KB
PCN03A-13 Alternate Qualified Assembly and Material Sets for Select Devices
PCN03A-13 6/28/2013 PDF 202.5 KB
PCN03A-14 Characterization Report
PCN03A-14 1.0 4/4/2014 PDF 919.5 KB
PCN06A-14 Affected Device List
PCN06A-14 1.0 10/3/2014 XLSX 45.1 KB
PCN06A-14 Material Set Table
PCN06A-14 1.0 10/3/2014 XLSX 13.7 KB
PCN06A-14 Characterization Report
PCN06A-14 1.0 10/3/2014 PDF 563.7 KB
PCN06B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and Alternate Qualified Material Sets for Select Lattice Products
PCN06B-14 1.0 11/21/2014 PDF 229.5 KB
PCN03A-14 FAQ
PCN03A-14 1.0 4/4/2014 PDF 452.5 KB
PCN03A-14 Material Set Table
PCN03A-14 1.0 4/4/2014 XLSX 26.9 KB
PCN03A-14 Affected Part Number List
PCN03A-14 1.0 4/4/2014 XLSX 60 KB
PCN03B-14 Notification of Intent to Utilize an Alternate Qualified Assembly Site/Test Site and/or Alternate Qualified Material Sets for Select Lattice Products
PCN03B-14 1.0 11/21/2014 PDF 229.9 KB
PCN06C-11 Withdrawal of PCN06B-11
Material Set 		PCN06C-11 1.0 8/1/2011 PDF 838.5 KB
ACN03D-11 Withdrawal of ACN03C-11
Material Set 		ANC03D-11 1 4/1/2011 PDF 796.6 KB
PCN07C-11 Withdrawal of PCN07B-11
Material Set 		PCN07C-11 1.0 8/1/2011 PDF 917.9 KB
PCN04B-11 Alternate Qualified Mask Set and Foundry for ispMACH 4000ZE
Mask Set 		PCN04B-11 1.0 7/21/2011 PDF 68.1 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Lattice OrCAD Capture Schematic Library (OLB)
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs. 		FPGA-SC-02005 8.2 8/8/2024 ZIP 2.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Product Selector Guide
I0211 46.0 7/18/2024 PDF 9.7 MB
ispMACH 4000ZE Product Brief (Japanese)
I0196J 7.0 9/28/2010 PDF 991 KB
ispMACH 4000ZE Pico Development Kit Product Brief
I0204 1.0 5/22/2013 PDF 1 MB
Automotive Solutions Product Brief
I0164 8.0 6/5/2009 PDF 2.4 MB
ispMACH 4000ZE Product Brief
I0196 7.0 4/30/2010 PDF 1.1 MB
ispMACH 4000ZE Product Brief (Chinese)
I0196C 8.0 11/19/2012 PDF 1.8 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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MN64_4kZE
Rev P1 6/21/2022 PDF 147.9 KB
TN_TG_TQ144 Cu_wire all
Rev E1 12/21/2021 PDF 107.1 KB
MN144_4kZE
Rev R1 6/21/2022 PDF 151.9 KB
TN_TG100 Cu_wire all
Rev D2 12/21/2021 PDF 25.4 KB
MN132_Cu_all
Rev R1 6/21/2022 PDF 149.6 KB
UMN132_4kZE
Rev Q1 6/21/2022 PDF 141.7 KB
TN48_4kZE
Rev D 5/2/2018 PDF 25.3 KB
UMN64_4kZE
Rev Q1 6/21/2022 PDF 141.6 KB
Lattice ispMACH4000 V/B/C/ZC/ZE Product Family Qualification Summar
G 10/1/2012 PDF 1.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Practical Low Power CPLD Design (Japanese Language)
1.0 6/28/2010 PDF 519.1 KB
White Paper: The Impact of Energy Efficiency Standards on Standby Power in Consumer Electronics Design
6/7/2010 PDF 87.1 KB
Practical Low Power CPLD Design (Chinese Language)
1.0 6/28/2010 PDF 461.6 KB
Practical Low Power CPLD Design (Traditional Chinese Language)
1/1/0001 PDF 551.2 KB
Practical Low Power CPLD Design (Korean Language)
1/1/0001 PDF 541.9 KB
Low Cost Board Layout Techniques for Designing with PLDs in BGA Packages (Chinese Language)
1.0 7/1/2010 PDF 488.5 KB
ispMACH 4000ZE Practical Low Power CPLD Design
8/25/2009 PDF 136.5 KB
ispMACH 4000ZE - Enabling CPLDs in Ultra High Volume, Low Power Applications
4/28/2008 PDF 178.5 KB
ispMACH 4000ZE - Enabling CPLDs in Ultra High Volume, Low Power Applications (Chinese Language)
1.0 6/8/2009 PDF 396.3 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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ispMACH 4032ZE CSBGA 64
1.01 7/19/2010 BSM 13.2 KB
[BSDL] ispMACH 4032ZE TQFP 48
1.00 4/24/2008 BSM 12.8 KB
[BSDL] ispMACH 4256ZE TQFP 100
1.00 4/28/2008 BSM 24 KB
[BSDL] ispMACH 4064ZE CSBGA 64
1.00 4/28/2008 BSM 17 KB
[BSDL] ispMACH 4064ZE TQFP 48
1.00 4/28/2008 BSM 16.3 KB
[BSDL] ispMACH 4256ZE TQFP 144
1.00 4/28/2008 BSM 25.7 KB
[BSDL] ispMACH 4128ZE UCBGA 132
1.00 4/28/2008 BSM 22.1 KB
[BSDL] ispMACH 4128ZE TQFP 100
1.00 4/28/2008 BSM 20.9 KB
[BSDL] ispMACH 4256ZE CSBGA 144
1.00 4/28/2008 BSM 25.7 KB
[BSDL] ispMACH 4128ZE TQFP 144
1.00 4/28/2008 BSM 22.2 KB
[BSDL] ispMACH 4128ZE CSBGA 144
1.00 4/28/2008 BSM 22.3 KB
[BSDL] ispMACH 4064ZE CSBGA 144
1.00 4/1/2008 BSM 18.5 KB
[BSDL] ispMACH 4064ZE TQFP 100
1.00 4/28/2008 BSM 17.9 KB
[BSDL] ispMACH 4064ZE UCBGA 64
1.00 4/28/2008 BSM 17.1 KB
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[IBIS] ispMach 4000ZE
1.1 12/9/2008 IBS 578.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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BGA Breakout and Routing Example #1 - MN144
TN1074 1.0 12/29/2009 ZIP 920.3 KB
ispMACH 4256ZE Breakout Board OrCAD Capture Schematic Source
Design Entry (.dsn) format schematics for the ispMACH 4256ZE Breakout Board. 		1.0 3/21/2011 DSN 384.5 KB
ispMACH 4256ZE Breakout Board PCB Artwork
PCB Design (.brd) format PCB artwork and PDF for the ispMACH 4256ZE Breakout board. 		1.0 3/21/2011 ZIP 3.9 MB
BGA Breakout and Routing Example #2 - MN144
TN1074 1.0 12/29/2009 ZIP 964 KB
BGA Breakout and Routing Example - UMN64
TN1074 1.0 12/29/2009 ZIP 815 KB
BGA Breakout and Routing Example - MN64
TN1074 1.0 12/29/2009 ZIP 791.2 KB

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