Single Wire Signal Aggregation Reference Design

PCB Congestion Relief using FPGAs for Signal Aggregation and Transmission Over Single Wire

Single-Wire is a single-ended single-wire connection between two FPGAs to provide TDM-based bidirectional communication, aggregating multiple data such as DP-AUX, I2C, I2S, and GPIO to add more flexibility to a customer’s system and board design. The design is targeted to the iCE40 UltraPlus™ device and compiled by the Lattice Radiant® software to generate a bit file. Hardware behavior is verified by aggregating multiple I2C and GPIO signals on the iCE40 UltraPlus Breakout Board. Hardware behavior on I2S is verified on the iCE40 UltraPlus MDP (Mobile Development Platform). Lastly, DP-Aux is verified in simulation.

Offers Solution to System Design Challenges – Connectors are the single highest contributor to system reliability. They also consume valuable PCB and system space, which is especially critical in hinged applications such as in notebooks. Single Wire Signal Aggregation allows you to reduce your connector and cable size while increasing your reliability.

Flexible & Robust Options – The single wire communication between the FPGAs is around 7.5 Mbps. The design is also configurable, the number of I2C/I2S busses and GPIOs and single wire protocol packet length can be adjusted. The single wire protocol between the FPGAs is robust with error detection and retry features.

FPGA Design Challenges – Field Programmable Gate Arrays (FPGAs) are amazing devices. With a little Hardware Description Language (HDL) skills you can craft these devices to do almost anything digital; video multiplexors, bus interfaces, motor controllers, this list is endless. But in the event that your team does not have these skills, you could be stuck. In the case of signal aggregation, we provide you with the FPGA bitstreams for a variety of popular configurations.

If your team has HDL skills and you want to customize our Single Wire Signal Aggregation Reference Design, we supply the source code as well.

Features

  • Up to 7 channels can be aggregated in total
  • Variable packet length for efficient use of the bandwidth
  • Supports an I2S Controller option to generate SCK and WS for the I2S transmit
  • Supports I2C at 100 kbps, fast-mode (400 kbps) and fast-mode plus (1 Mbps)
  • Raw data rate on Single-Wire is ~7.5 Mbps or higher depending on the target

Block Diagram

Resource Utilization

Configuration FPGA LUT FF EBR PLL I/O
CH#0: I2C (Master on M) M 545 261 0 1 7
CH#1: GPIO (1 bit Interrupt), S to M only S 626 286 0 1 7
CH#0: I2S M 892 449 1 1 13
CH#1: I2C (Master on M) S 1030 494 1 1 13
CH#2: I2C (Master on M)
CH#3: GPIO (4 bits), M to S only
CH#0: I2S M 1702 760 3 1 15
CH#1: DP Aux
CH#2: I2C (Master on M)
CH#3: I2C (Master on M) S 1719 814 3 1 15
CH#4: GPIO (4 bits), M to S, S to M

Note: M denotes Master FPGA. S denotes Slave FPGA.

Documentation

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.