Single Wire Signal Aggregation Reference Design

PCB congestion relief using FPGAs for signal aggregation and transmission over single wire

PCB design challenges – In many systems processors use multiple interfaces including I2C, GPIO, and I2S to collect data from peripherals and sensors. In some of these systems PCB real estate is a premium in addition designers are going with smaller PCBs that connect together to fit into neat looking industrial designs. Routing signals through congested PCBs and connectors presents some challenges.

SWA Award

System Design Challenges – Connectors are the single highest contributor to system reliability. They also consume valuable PCB and system space, which is especially critical in hinged applications such as in notebooks. Single Wire Aggregation allows you to reduce your connector and cable size while increasing your reliability.

Flexible & robust options – The single wire communication between the FPGAs is around 7.5 Mbps. The design is also configurable, the number of I2C/I2S busses and GPIOs and single wire protocol packet length can be adjusted. The single wire protocol between the FPGAs is robust with error detection and retry features.

FPGA Design Challenges – Field Programmable Gate Arrays (FPGAs) are amazing devices. With a little Hardware Description Language (HDL) skills you can craft these devices to do almost anything digital; video multiplexors, bus interfaces, motor controllers, this list is endless. But in the event that your team does not have these skills, you could be stuck. In the case of signal aggregation, we provide you with the FPGA bitstreams for a variety of popular configurations.

If your team has HDL skills and you want to customize our Single Wire Aggregation Reference Design, we supply the source code as well.


  • No FPGA tools knowledge necessary
  • Up to 7 channels can be aggregated
  • Raw data rate on single wire is ∼7.5 Mbps or higher
  • Variable packet length for efficient use of the single wire bandwidth
  • Retransmit feature is offered when parity error is detected on RX side
  • Supports I2C Fast-mode (400 kbps) and Fast-mode Plus
  • I2S supports single stereo channel, 48 khz sampling rate, up to 32 bits per sample with bi-directional support

Block Diagram

Signal Aggregation De-Aggregation


Technical Resources
Information Resources
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Single Wire Aggregation - Source Code
1.2 9/28/2020 ZIP 27.3 MB
Single Wire Signal Aggregation - Documentation
FPGA-RD-02039 1.2 9/9/2020 PDF 2.3 MB
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FPGA-Based Single Wire Aggregation (SWA) for FPGA and Non-FPGA Designers
WP0026 1.0 9/16/2020 PDF 845.1 KB

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