Single Wire Signal Aggregation Development Board

PCB Congestion Relief using FPGAs for Signal Aggregation and Transmission Over Single Wire

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The Lattice Single Wire Signal Aggregation Development Board is based on iCE40 UltraPlus™ FPGA chip but is designed to be easily portable to other iCE40 and Lattice FPGAs. The device is iCE40 UltraPlus SRAM-based FPGA with on-chip, one-time programmable NVCM (Non-Volatile Configuration Memory) to store configuration data. The SRAM memory cells are volatile, meaning that once power is removed from the device, its configuration is lost, and must be reloaded on the next power-up. This behavior has the advantage of being re-programmable in the field, which provides flexibility for products already deployed to the field, but it also requires that the configuration information be stored in a non-volatile device and loaded each time power is applied to the device.

The on-chip NVCM allows the device to configure instantly and enhances the design security by eliminating the need to use an external memory device. The configuration data can also be stored in an external SPI Flash from which the FPGA can configure itself upon power-up. This is useful for prototyping the FPGA or in situations where re-configurability is required. Additionally, the device can be configured by a processor in an embedded environment.

Connectors are the single highest contributor to system reliability. They also consume valuable PCB and system space, which is especially critical in hinged applications such as in notebooks. Single Wire Signal Aggregation allows you to reduce your connector and cable size while increasing your reliability

Single Wire Prototyping – Two boards are provided can be re-configured to interface to a prototype system to demonstrate the proof of concept in-system.

Supports Non-Volatile Configuration Memory – Provides the capability for iCE devices to perform in a stand-alone mode, essentially behaving like an ASIC. The NVCM is ideal for cost-sensitive, high-volume production applications, saving the cost and board space associated with an external configuration PROM.


  • Raw data rate on Single-Wire is configurable as ~7.5 Mbps or higher
  • Supports I2C at 100 kpps, Fast-Mode (400 kbps) and Fast-Mode Plus (1 Mbps)
  • I2C Interrupt can be realized by GPIO with event-based transmission
  • Each channel can be either I2C, I2S or GPIO
  • Board set can be configured as a stand-alone demo or in-system proof of concept

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SWA Board Overview
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SWA Board Overview

Board Photos

Bottom View

Side View

Ordering Information

  • Ordering Part Number: iCE40UP5K-SWA-EVN
  • Click here to find an authorized Lattice distributor near you


Quick Reference
Technical Resources
Information Resources
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Single Wire Signal Aggregation User Guide
FPGA-UG-02117 1.1 5/1/2023 PDF 3.9 MB
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Single Wire Signal Aggregation Reference Design - Source Code
1.2 9/28/2020 ZIP 22.5 MB
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FPGA-Based Single Wire Aggregation (SWA) for FPGA and Non-FPGA Designers
WP0026 1.0 9/16/2020 PDF 845.1 KB
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Single Wire Signal Aggregation Development Board - Gerber Files
1.0 9/10/2020 ZIP 1.2 MB

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Custom Design Requests

Custom Designs

Click here to request a quick-turn custom Single Wire Signal Aggregation via our technical support system.

Please file a technical support request here.

File Under:

  • Case Type: Reference Design
  • Case Category: Single Wire Signal Aggregation Customization Request


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