CSI-2/DSI D-PHY Receiver IP Core

Convert MIPI CSI-2/DSI Data Streams to Parallel Data

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The Lattice Semiconductor CSI-2/DSI D-PHY Receiver IP Core converts DSI or CSI-2 data to 8-bit, 16-bit, 32-bit, or 64-bit data for Lattice FPGA devices built on the Lattice Avant™, Nexus™, and Nexus 2 platforms. The CSI-2/DSI D-PHY Receiver IP Core is intended for use in applications that require a D-PHY receiver in the FPGA logic. D-PHY Rx IP includes in both the high-speed and low power modules.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Compliant with MIPI D-PHY v1.2, MIPI DSI v1.1, and MIPI CSI-2 v1.2 specifications.
  • Selection between Hard Rx D-PHY or Soft Rx D-PHY implementation. Hard Rx D-PHY is only available for CrossLink-NX devices.
  • Supports MIPI DSI and MIPI CSI-2 interfaces up to 6 Gb/s for Soft D-PHY and up to 10 Gb/s for Hard D-PHY.
  • Supports 1, 2, 3, or 4 data lanes and one clock lane

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Block Diagram

CSI-2/DSI D-PHY Receiver

Resource Utilization

IP Configuration for Nexus Family
Lane
(Gear)		 RX Interface Type IP Type Bit Rate
(Lane) 		Parser AXI Bus LMMI Bus Registers LUT2 EBR High-Speed I/O esources
4(8) CSI-2 Hard D-PHY4 1000 Mbps EN EN DIS 629 699 2 1 x Hard D-PHY
4(8) CSI-2 Soft D-PHY 1000 Mbps EN EN DIS 706 1212 2 4 x IDDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4(16)3 CSI-2 Hard D-PHY4 2500 Mbps EN EN DIS 852 991 4 1 x Hard D-PHY
4(8)3 CSI-2 Soft D-PHY4 1500 Mbps EN EN DIS 706 1270 2 4 x IDDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4(16) DSI Hard D-PHY4 2000 Mbps EN EN EN 1006 1520 4 1 x Hard D-PHY
4(16) DSI Hard D-PHY5 2000 Mbps EN EN EN 1006 1520 4 1 x Hard D-PHY
4(8) DSI Hard D-PHY4 1200 Mbps EN EN DIS 682 843 2 1 x Hard D-PHY
2(8) DSI Hard D-PHY4 800 Mbps EN DIS DIS 448 566 2 1 x Hard D-PHY
4(16)3 CSI-2 Hard D-PHY4 2500 Mbps EN EN EN 870 1041 4 1 x Hard D-PHY
4(8)3 CSI-2 Hard D-PHY4 1500 Mbps EN EN EN 585 747 2 1 x Hard D-PHY
2(8) CSI-2 Hard D-PHY4 800 Mbps EN DIS DIS 447 554 2 1 x Hard D-PHY

1. All other settings are default.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.
3. Data Settle settings were changed in these configurations to match their target Bit Rate per Lane.
4. Hard D-PHY – CIL Bypassed
5. Hard D-PHY – CIL Enabled
For more information regarding a specific configuration, the user can generate the IP, run synthesis and MAP, and check the MAP reports for resource utilization.

To view the complete Resource Utilization of the CSI-2/DSI D-PHY Receiver IP Core, click here to view the table.

Ordering Information

The CSI-2 DSI D-PHY Receiver core is available for FREE for use in Diamond design software.

For Radiant design software, the CSI-2 DSI D-PHY Receiver core must be purchased:

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Certus-N2 DPHY-RX-CN2-UT DPHY-RX-CN2-US
Avant-G DPHY-RX-AVG-UT DPHY-RX-AVG-US
Avant-X DPHY-RX-AVX-UT DPHY-RX-AVX-US
Avant-E DPHY-RX-AVE-UT DPHY-RX-AVE-US
MachXO5-NX DPHY-RX-XO5-UT DPHY-RX-XO5-US
CertusPro-NX DPHY-RX-CPNX-UT DPHY-RX-CPNX-US
CrossLink-NX DPHY-RX-CNX-UT DPHY-RX-CNX-US
Certus-NX DPHY-RX-CTNX-UT DPHY-RX-CTNX-US
Bundled MIPI-BNDL-UT MIPI-BNDL-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the CSI-2/D-PHY Receiver IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CSI-2/DSI D-PHY Rx IP User Guide
FPGA-IPUG-02081 2.3 12/20/2024 PDF 1.9 MB
CSI2/DSI D-PHY Receiver IP Core User Guide for Diamond Design Software
FPGA-IPUG-02025 1.5 11/24/2021 PDF 1.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CSI-2/DSI D-PHY Rx IP Release Notes
FPGA-RN-02040 1.0 12/20/2024 PDF 199.1 KB

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