[Blog] Design Faster and Smarter: What’s New in Lattice Radiant and Propel (version 2025.1)

Given the broad range of roles Lattice Field Programmable Gate Arrays (FPGAs) play in modern systems—like industrial robotics, automotive networking, communications infrastructure, and beyond—there are countless ways for system and application designers to leverage our silicon.

To streamline FPGA adoption, we offer best-in-class, easy-to-use software solutions with a variety of helpful design features. These software offerings include the Lattice Radiant™ software and  design environment, both of which provide powerful tools for designing, creating, debugging, and implementing FPGA-based systems. With new updates in the 2025.1 versions, Radiant and Propel offer developers and designers a suite of new and improved capabilities for leveraging FPGAs.

Key Lattice Radiant 2025.1 Feature Updates
Lattice Radiant offers best-in-class tools for efficient and effective FPGA application design. It leverages a design constraints flow and continuous timing analysis to ensure optimal results, all through an intuitive, modular, and wizard-driven unified design database. Given its capabilities, Radiant is best suited for supporting FPGA applications in the Industrial, Communications, Automotive, Computing, Defense, and Consumer industries.

The Lattice Radiant 2025.1 release is geared specifically towards helping designers realize their creativity and maximize their productivity for small and mid-range FPGA designs.

Its top capabilities include:

• Faster verification cycles.
  The faster you can test and verify the effectiveness of your FPGA design, the faster you can deploy devices in the field. Streamlined Radiant verification cycles enable faster time-to-market, earlier error detection and remediation, and enhanced productivity for design teams.
  A new External Memory Controller Debug feature enables the fast bring-up of double data rate (DDRx) memory interfaces and supports more efficient cycles. Faster waveform capture and review offered by the trace history capability of the Radiant Reveal tool enable further increases in efficiency. These updated capabilities make FPGA design less time-consuming, improving the overall Lattice Nexus™ based FPGA devices compile time by 25%. 
• Optimized user experience.
  The new UX features in Lattice Radiant include a percentage (%) view in both the Report Summary and Run Manager, which enables quick access to resource utilization information. A runtime breakdown is also implemented for each compilation stage to help improve designer efficiency. Beyond this, the PAR report is enhanced with Virtual I/O visibility and provides a new tabular format for compilation reports to make organizing and reading reports easier.
• Increased design productivity.
  The latest release includes a simplified process for setting virtual pins by setting Virtual I/O on all ports during the Map design stage, helping to streamline block-based design strategies. It also includes an overall improvement to the Lattice Nexus FPGA design experience, with designers experiencing a 4.5% improvement in Nexus quality of results (QoR).
  

Key Lattice Propel 2025.1 Feature Updates
The Lattice Propel design environment provides users with a complete set of graphical and command-line tools to help them create, analyze, compile, and debug both the hardware and software that make up an FPGA-based processor system.

The Lattice Propel 2025.1 release is built to simplify and streamline embedded system design processes for FPGA devices. This design software has wide-ranging features, meant to support all designers of embedded FPGA solutions across industries.

New 2025.1 capabilities include:

• Accelerated project start-up.
  FPGA designers should, ideally, be able to get started on their designs in minutes. With new system-on-chip (SoC) project and single-function application templates built into the Propel software, both hardware and software engineers can start developing embedded designs much faster. This allows for the quick creation of RISC-V® SoC low power mode and multiple processor designs.
  
• Intuitive design creation.
  Beyond start-up, the design experience itself should be as seamless as possible for both hardware and software designers. Propel now offers the ability to easily port existing designs from one device to another using the new Porting Project feature. Its embedded debug options are now expanded with SoC memory data read/write capabilities via JTAG Bridge IP and a Lattice HW-USBN-2B cable using TCL. Lastly, Propel has simplified the IP import process via new IP Packager and IP Upgrade capabilities.
  

Designing and Developing FPGAs with Ease

The 2025.1 updates to Lattice Radiant and Propel are designed with one goal in mind: to make FPGA design more accessible, efficient, and powerful. With improved ease of use and enhanced capabilities, users can efficiently design and deploy FPGAs with capabilities to support a range of key use cases.

Learn more about our latest software offerings and contact our team today to explore how the latest Lattice software updates can support your next FPGA project.