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Latest Automotive and Industrial News from Lattice

Q2 2019 Industrial and Automotive Newsletter
Posted 06/28/2019 by Lattice Semiconductor

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New FPGA Brings Root-of-Trust Capability to Firmware

It’s a dangerous world out there. Hackers are continually taking advantage of unsecure systems to steal data and design info, clone or overbuild components, and tamper with or hijack devices. In 2018 alone, analysts estimate that hackers took advantage of security vulnerabilities in firmware to render over three billion chips of all types open to data theft. Moreover, these attacks can occur at any stage of the product lifecycle from the point of manufacturing to the system’s end-of-life.

But the news is not all bad. Now you can add a new weapon to your security arsenal. Lattice has announced the MachXO3D, a new FPGA family that simplifies the implementation of comprehensive, flexible and robust hardware security throughout the product lifecycle. The MachXO3D is the first small, low power FPGA for system control applications designed to secure system firmware across a wide array of applications including computing, communications, industrial control and automotive. With it designers can establish one or more root-of-trust devices which can be used as a platform to provide cryptographic capabilities that secure their systems. Representative of its robust design, the MachXO3D is the industry’s first control-oriented FPGA to comply with NIST’s SP 800 193 Platform Firmware Resiliency (PFR) guidelines. It is also pin-compatible with Lattice’s popular MachXO3 architecture, simplifying retrofitting or the addition of new security features into existing control solutions. Check out our white paper on hardware security to learn how the MachXO3D can help you build more secure systems.


CrossLink Bridge Offers Access to Mobile Processors

One of the ongoing challenges designers of automotive and industrial systems face today is how can they can take advantage of the high performance and low cost of MIPI processors in systems that still rely heavily on legacy cameras, displays and interfaces. In many cases the cameras and displays used on embedded systems don’t match the type or number of interfaces on mobile processors. Fortunately, Lattice has the interface bridge reference design you need to address this problem. Using our new MIPI DSI/CSI -2 to OpenLDI LVDS bridge reference design for CrossLink, you can quickly create a bridging solution and configure it to specific interface requirements. The reference design is free and can be used to quickly and easily demonstrate Lattice’s popular IPs for applications like Byte-to-Pixel conversion, CSI-2/DSI D-PHY receivers and FPD-LNK (OpenLDI) transmitters. The bridge comes in various configurations including single CSI-2 input to single or dual channel LVDS outputs and single DSI input to single or dual channel LVDS outputs. It supports MIPI DSI inputs up to 1.5 Gbps per lane as well as OpenLDI at 1.2 Gbps per lane. The bridge is fully compliant with the CSI-2 v 1.1 and the DSI v 1.1 specifications.

MIPI DSI to OpenLDI LVDS Image Sensor Bridge Block Diagram

Demo Showcases Enhanced 3D Mapping

Want to see how Lattice’s new 3D Depth Mapping demo utilizes the extensive computing capabilities of our ECP5 FPGAs in auto collision avoidance and factory automation sensor apps running at the network edge? Then check out our new demo. It uses a Semi Global Block-Matching (SGBM) algorithm to determine 64 different disparity levels which can be used to determine the distance between an embedded device and an object. The demo buffers incoming video in DDR memory and performs rectification to separate the left and right video images to calculate a common plane. The output signal is then transmitted via a HDMI interface. The demo supports input of up to 1080p @ 60fps stereo video and output of 320 x 240 @ 60 fps depth map with 64 depth levels. The demo consumes less than 1 W of power in the ECP5. Source files are available upon request.

3D Depth Mapping Block Diagram

Video Scaling Got You Down?

Having trouble efficiently scaling video from one size for video input to another for video output? Consider your problem solved. Lattice’s new Scaler IP core for the ECP5 offers a highly flexible architecture that supports a wide variety of scaling algorithms and a highly configurable design that takes advantage of the embedded DSP blocks in Lattice’s FPGAs. Designers can use a simple I/O handshake to make the core suitable for either streaming video or bursts of input video. They can also update in-system input and output frame size on a frame basis. The new IP also supports multi-color plane (RGB and YCbC4:4:4), serial filtering and multi-scaling algorithms. It also offers a configurable number of filter taps for Lanczos coefficient sets and a configurable number of phases for Bicubic, Mitchell and Lanczos coefficient sets.

2D Scaler IP Core

Lattice Diamond Adds Support for MachXO3D

The latest version of Lattice’s Diamond software v 3.11, offers new features that promise to dramatically improve design flows and enhance hardware security. Version 3.11 of the GUI-based FPGA design and verification environment now supports Lattice’s recently announced MachXO3D FPGAs which are designed to improve hardware security throughout the product lifecycle by adding Root-of-Trust (RoT) capability. As systems become increasingly complex and vulnerable to data and design theft, hijacking, data corruption and counterfeiting, the MachXO3D FPGA helps designers quickly and easily implement flexible and robust hardware security. At the same time Diamond 3.11 also features the popular Synplify Pro Logic synthesis solution to help manage larger FPGA designs. In this version of Diamond, the synthesis tool helps designers who want to input their desired maximum frequency (Fmax) as a design constraint to improve optimization and performance. For Linux users Lattice’s Diamond 3.11 now supports RedHat Linux version 6.9 and 7.

Lattice Diamond 3.11