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Reference Design

UART Reference Design

The UART reference design describes a fully configurable UART optimized for and implemented in a variety of Lattice devices.

Reference Design

UART 16550 Transceiver

Implements a UART compatible to PC16550 in FPGA.

IP Core

UART IP Core

Propel IP Module: Similar to NS16450 UART for serial communication supporting RS-232.

Reference Design

8N1 UART Transceiver Reference Design

8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU

IP Core

UART 16550 IP Core

​​Lattice UART16550 IP Core is designed for use in serial communication, supporting the RS-232, RS-422, RS-485, and Electronic Industries Association (EIA) standards, among others.​

IP Core

D16550: Configurable UART with FIFO

Soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A

IP Core

D16750: Configurable UART with FIFO

Soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C750.

IP Core

D16450: Configurable UART

Soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C450.

Reference Design

UART Reference Design - WISHBONE Compatible

UART (Universal Asynchronous Receiver/Transmitter) provides both Rx and Tx between the WISHBONE system bus and an RS232 serial communication channel.

IP Core

UART with FIFOs and Synchronous CPU Interface Core

A standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device

FAQ

UART Ip Core version 1.2 or earlier: Does the UART IP core in Lattice Propel Buldier support back-to-back transmission?

Yes, Back-to-back transmission is supported.

FAQ

UART 16550 IP Core: What is the custom baud rate support range for UART 16550 Propel IP Core?

Description:UART 16550 Propel IP Core supports custom baud rate in the range of 2400 to 1000000, which is stated in IP GUI custom baud rate parameter.There is a known documentation bug where custom baud rate supported was stated as 1 to 999999 which is incorrect.Solution:This documentation…

FAQ

How to determine UART pin direction of the on-chip FTDI for Lattice Boards?

Lattice boards use the FTDI chip for onboard debugging and programming. One of the interfaces that can be used is the UART port.To easily identify FPGA port assignments for UART, users can refer below information.TXD_UART (BDBUS0) is an output/transmitter pin on the FTDI side;…

FAQ

Lattice Mico System: Can user deploy LatticeMico32 code to a non-volatile memory with the JTAG UART active?

Lattice Mico System: The LatticeMico32 Software Project Environment (SPE) provides a framework for interfacing to functions defined in the stdio.h library. Functions like fopen, fread, printf, and fclose are, by default, tied to the JTAG UART. The JTAG UART permits the functions…

FAQ

Propel: How to bring up serial UART terminal for Propel RiscV project with MachXO5\u2122-NX Development Kit?

Description:This bring up guideline is based on Propel Builder default hello world template.Hardware setup pre-requisites1.       Power up the development kit with USB header (J19) instead of 12V power.2.       Removed JP8 and JP9 reset jumper to enable USB FTDI for both User USB header and Config…

FAQ

UART IP Core version 1.2 or earlier: How much deviation between the transmitter and receiver is allowed if it is 5% or 3%?

We don't have specific or Hardware tested deviation allowed; if the user plans to use UART IP, let's achieve minimal to zero deviation to ensure a reliable UART transaction.

FAQ

How can I use UART + JTAG access to FTDI chip on Linux?

There is no specific driver to support both JTAG and UART on FTDI Chips. You can only access to USB mode or UART mode at a time, there is no specific setting needed to support both JTAG + UART under LINUX for FTDI chips.

FAQ

Lattice Mico: In a Mico System Builder(MSB) project, can the characters transmitted through the UART be displayed on the Simulator console?

Description:Yes. The characters transmitted through the UART can be displayed on the Simulator console window during simulation. To enable this: double click the UART component in the hardware platform of MSB on the 'transmit Settings for RTL Simulation' settings, check the boxes,…

Reference Design

SPI-to-UART Expander

Acts as a SPI port expander, multiplexing and demultiplexing read/write data through the SPI slave to multiple UARTs

Document

IRDA UART TX

Design File ZIP 16.9KB