The Lattice Semiconductor DDR Memory Controller IP provides a turnkey solution consisting of a controller, DDRPHY, and associated clocking and training logic to interface with DDR4 and LPDDR4 SDRAM.
This IP supports all the Lattice Nexus 2, Avant, and Nexus device families for the following modes:
DDR4 and LPDDR4 mode:
Lattice Avant (Avant-E, Avant-G, Avant-X) and Lattice Nexus 2 (Certus-N2)
LPDDR4 mode only:
Lattice Nexus (CertusPro-NX, MachXO5T-NX)
Resource Utilization details are available in the DDR Memory Controller IP Core User Guide and LPDDR4 Memory Controller IP Core for Nexus Devices User Guide.
Check out the automated DDR pinout generation tool for Lattice Nexus and Avant FPGAs.
Features
DDR4 mode (Avant and Nexus 2)
- DDR4 SDRAM protocol, compliant to DDR4 JEDEC Standard.
- DDR4 SDRAM speeds up to 1200 MHz/2400 Mbps for speed grade 3 devices, up to 1066 MHz/2133 Mbps for speed grade 2, and up to 933 MHz / 1066 Mbps for speed grade 1.
(Dual-rank configurations are only supported on speed grades 2 and 3) - Component support for interface data widths of x16, x32, and x64.
- Up to 16 Gb density support.
LPDDR4 mode (Avant and Nexus 2)
- LPDDR4 SDRAM protocol, compliant to LPDDR4 JEDEC Standard.
- LPDDR4 SDRAM speeds up to 1200 MHz/2400 Mbps for speed grade 3 devices and up to 1066 MHz/2133 Mbps for speed grade2, and up to 933 MHz / 1066 Mbps for speed grade 1.
(Dual-rank configurations are only supported on speed grades 2 and 3) - Component support for interface data widths of x16, x32, and x64.
- Up to 16 Gb density support per channel
LPDDR4 mode (Nexus)
- LPDDR4 SDRAM protocol, compliant to LPDDR4 JEDEC Standard.
- LPDDR4 SDRAM speeds up to 533 MHz/1066 Mbps for speed grades 8 and 9, and up to 400 MHz/800 Mbps for speed grade 7
(Dual-rank configurations are supported up to 400 MHz/800 Mbps) - Component support for interface data widths of x16 and x32.
- Up to 16 Gb density support per channel
