Flash memory, whether it is in NOR or NAND in structure, is a non-volatile memory that is used to replace traditional EEPROM and hard disks for its low cost and versatility. Because of the difference in the structure of interconnection of the memory cells, NOR Flash is known for its random access capability, while the NAND Flash is known for its compact size. This is especially important in applications where the highest-density memory is offered in the smallest footprint.
This reference design is targeted at the Samsung K9F1G08R0A NAND Flash. It supports the reset, read ID, block erase, page program and page read commands. The read status command is supported for the program and erase operations. The other commands are not implemented in this design. This design implements a simple host interface which gives the designer the flexibility to modify this interface to meet the requirements of their host interface system.
|Tested Devices*||Language||Performance||I/O Pins||Design Size||Revision|
|LCMXO2-1200HC-4TG144CES||Verilog||> 80 MHz||69||434 LUTs, 2 EBRs||1.2|
|LCMXO2-1200HC-4TG144CES||VHDL||> 80 MHz||69||398 LUTs, 2 EBRs||1.2|
|LCMXO2280C-5T100C||Verilog||> 80 MHz||69||455 LUTs, 2 EBRs||1.2|
|LCMXO2280C-5T100C||VHDL||> 80 MHz||69||459 LUTs, 2 EBRs||1.2|
|LFXP2-5E-7M132C||Verilog||> 80 MHz||69||519 LUTs, 1 EBR||1.2|
|LFXP2-5E-7M132C||VHDL||> 80 MHz||69||515 LUTs, 2 EBRs||1.2|
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.